Patents by Inventor Kazuya Ishioka

Kazuya Ishioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120326774
    Abstract: A switching circuit according to one embodiment includes: a switching element that has a first terminal and a second terminal, and is driven by a pulse signal to switch a conduction state between the first and second terminals; a power source section that supplies a voltage to the first terminal; a load circuit that is connected in parallel with the power source section; a passive circuit section that is connected between a connection point between the power source section and the load circuit, and the first terminal, and suppresses a current flowing from the connection point to the switching element at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse signal; and a resonant circuit section that is connected between the passive circuit section and the connection point, and resonates at the frequency of N times.
    Type: Application
    Filed: June 27, 2012
    Publication date: December 27, 2012
    Applicants: National University Corporation TOYOHASHI UNIVERSITY OF TECHNOLOGY, Sumitomo Electric Industries, Ltd.
    Inventors: Satoshi HATSUKAWA, Nobuo SHIGA, Kazuhiro FUJIKAWA, Takashi OHIRA, Kazuyuki WADA, Tuya WUREN, Kazuya ISHIOKA, Kazushi SAWADA, Hiroshi Ishioka
  • Publication number: 20120306563
    Abstract: A switching circuit according to one embodiment is a switching circuit including at least one semiconductor switch element having an input, output, and a common terminals, a pulse-like signal being applied between the input and common terminals to switch a current between the output and common terminals. The switching circuit further includes a capacitance suppression element section connected at least one of between the input and output terminals, between the input terminal common terminals, and between the output and common terminals. The capacitance suppression element section reduces a parasitic capacitance between the terminals of the semiconductor switch element where the capacitance suppression element section is connected to less than that obtained when the capacitance suppression element section is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 6, 2012
    Applicants: National University Corporation TOYOHASHI UNIVERSITY OF TECHNOLOGY, Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro FUJIKAWA, Nobuo Shiga, Takashi Ohira, Kazuyuki Wada, Kazuya Ishioka, Hiroshi Ishioka
  • Publication number: 20120306288
    Abstract: A switching circuit according to one embodiment includes first to fourth semiconductor switch elements. A pulse-like signal is applied to each input terminal of the switch elements such that when the first and fourth switch elements are in an ON (OFF) state, the remaining switch elements are in an OFF (ON) state. The switching circuit includes first and second capacitance elements. The first capacitance elements connected between an output terminal of the second semiconductor switch element and the second capacitance elements connected between an input terminal of the second semiconductor switch element and an output terminal of the fourth semiconductor switch element has a capacitance to reduce a parasitic capacitance between the input and output terminals of each of the fourth and second switch elements at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 6, 2012
    Applicants: National University Corporation Toyohashi University Of Technology, Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Nobuo Shiga, Takashi Ohira, Kazuyuki Wada, Kazuya Ishioka, Hiroshi Ishioka