Patents by Inventor Kazuya Isono

Kazuya Isono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240170825
    Abstract: This filter comprises: a dielectric substrate; a plurality of resonators that are formed inside the dielectric substrate, and for which the periphery is surrounded by a shielding conductor; and input/output terminals that are formed at a portion at which the shielding conductor is not formed. The resonator closest to the input/output terminal of the plurality of resonators and the resonator that is closest to the input/output terminal of the plurality of resonators are in a point-symmetrical positional relationship.
    Type: Application
    Filed: February 28, 2022
    Publication date: May 23, 2024
    Applicant: SOSHIN ELECTRIC CO., LTD.
    Inventors: Yoshiharu IMAI, Yuichi MIYATA, Genta NISHIO, Shun SUZUKI, Kazuya ADACHI, Hiroyuki ISONO, Kazuma KOSAKA
  • Publication number: 20070286039
    Abstract: An off-track state is to be detected accurately. A photodetector 11 converts the light reflected from an optical disc into an electrical signal. A MIRR signal generating circuit 16 generates a bi-level MIRR signal 23, indicating whether the photodetector 11 is in an on-track state or an off-track state with respect to a track of the optical disc, based on an output signal of the photodetector 11. A TEC signal generating circuit 17 generates a bi-level TEC signal 24, indicating whether the photodetector 11 is on an inner side or on an outer side in the radial direction of the optical disc with respect to the track in the optical disc currently closest to the photodetector, based on the output signal of the photodetector 11. An off-track detector 18 outputs an off-track signal 25 if, after the level of the MIRR signal 23 is changed from an on-track state to an off-track state, the level of the TEC signal 24 is changed without the level of the MIRR signal 23 being changed.
    Type: Application
    Filed: May 23, 2007
    Publication date: December 13, 2007
    Inventor: Kazuya Isono
  • Patent number: 5270713
    Abstract: In a decode circuit comprising a decoding section for decoding an input signal in response to a controlled clock signal into an intermediate signal having a variable pattern, the decode circuit comprises a clock generator section for generating first through N-th clock signals having first through N-th phases different from one another, respectively, where N represents a positive integer which is not less than two. The first through the N-th clock signals are selectively used as the controlled signal. When the variable pattern of the intermediate signal is identical with a predetermined pattern, a coincidence detecting section supplies the detecting section with a selected one of the first through the N-th clock signals as the controlled clock signal. When the variable pattern of the intermediate signal is identical with the predetermined pattern in the coincidence detecting section, an output section allows the intermediate signal as an output signal to pass therethrough.
    Type: Grant
    Filed: July 24, 1992
    Date of Patent: December 14, 1993
    Assignee: NEC Corporation
    Inventor: Kazuya Isono