Abstract: A manufacturing method of an epitaxial silicon wafer includes forming an epitaxial film made of silicon on a surface of a silicon wafer in a trichlorosilane gas atmosphere; and setting the nitrogen concentration of the surface of the epitaxial film through inward diffusion from a nitride film on the epitaxial film, the nitride film being formed by subjecting the silicon wafer provided with the epitaxial film to heat treatment in a nitrogen atmosphere.

Abstract: A manufacturing method of an epitaxial silicon wafer includes forming an epitaxial film made of silicon on a surface of a silicon wafer in a trichlorosilane gas atmosphere; and setting the nitrogen concentration of the surface of the epitaxial film through inward diffusion from a nitride film on the epitaxial film, the nitride film being formed by subjecting the silicon wafer provided with the epitaxial film to heat treatment in a nitrogen atmosphere.

Abstract: Provided is a terminal plate according to an embodiment including: a first plate portion for being connected to a first semiconductor element; a second plate portion for being connected to a second semiconductor element; a third plate portion provided above the first plate portion and the second plate portion; a first connecting portion provided between the first plate portion and the third plate portion and connecting the first plate portion and the third plate portion; a second connecting portion provided between the second plate portion and the third plate portion and connecting the second plate portion and the third plate portion; a fourth plate portion provided above the first plate portion and the second plate portion and provided on the opposite side of the third plate portion with interposing the first and second plate portions; a third connecting portion provided between the first plate portion and the fourth plate portion and connecting the first plate portion and the fourth plate portion; a fourth

Abstract: A semiconductor device including a main board; a first board provided on the main board; first and second semiconductor elements provided on the first board; a first positive terminal provided on the first board; a first negative terminal provided on the first board; a first output terminal provided on the first board; a second board provided on the main board; third and fourth semiconductor elements provided on the second board; a second positive terminal provided on the second board; a second negative terminal provided on the second board; a second output terminal provided on the second board; a first terminal plate connecting the first positive terminal and the second positive terminal, a second terminal plate connecting the first negative terminal and the second negative terminal, and a third terminal plate connecting the first output terminal and the second output terminal.

Abstract: Provided is a semiconductor device according to an embodiment including: a main board; a first board provided on the main board; a second board provided on the main board; a first electrode member provided on the first board and having a first planar portion; a second electrode member provided on the first board and having a second planar portion; a third electrode member provided on the first board and having a third planar portion; a first semiconductor element provided on the first electrode member and having a first electrode and a second electrode; a second semiconductor element provided on the second electrode member and having a third electrode and a fourth electrode; a first wire electrically connecting the second electrode and the second electrode member; a second wire electrically connecting the fourth electrode and the third electrode member; a fourth electrode member provided on the second board and having a fourth planar portion; a fifth electrode member provided on the second board and having a

Abstract: Provided is a terminal plate according to an embodiment including: a first plate portion for being connected to a first semiconductor element; a second plate portion for being connected to a second semiconductor element; a third plate portion provided above the first plate portion and the second plate portion; a first connecting portion provided between the first plate portion and the third plate portion and connecting the first plate portion and the third plate portion; a second connecting portion provided between the second plate portion and the third plate portion and connecting the second plate portion and the third plate portion; a fourth plate portion provided above the first plate portion and the second plate portion and provided on the opposite side of the third plate portion with interposing the first and second plate portions; a third connecting portion provided between the first plate portion and the fourth plate portion and connecting the first plate portion and the fourth plate portion; a fourth

Abstract: A manufacturing method of an epitaxial silicon wafer includes: an epitaxial-film formation step for forming an epitaxial film made of silicon on a surface of a silicon wafer in a trichlorosilane gas atmosphere; and a nitrogen-concentration setting step for setting the nitrogen concentration of the surface of the epitaxial film through inward diffusion from a nitride film on the epitaxial film, the nitride film being formed by subjecting the silicon wafer provided with the epitaxial film through the epitaxial-film formation step to a heat treatment in a nitrogen atmosphere.

Abstract: A semiconductor modules includes insulating substrates having first and second patterns thereon. One terminal plate connects the first patterns and another terminal plate connects the second patterns. A first and a second switching chip are provided on the first pattern. Bonding wires connect the first ans second chips to the second pattern. An insulating plate with an auxillary conductor theron is disposed on the first pattern between the second pattern and both the first and second chips. A first auxiliary connection connect the auxiliary conductor and the second chip and a second auxilliary connection connect thes auxiliary conductor and the second pattern. The auxiliary connections may be, for example, bonding wires or solder connections.

Abstract: A semiconductor device includes a base plate, a semiconductor chip, and a first to a fourth terminal plates. The first terminal plate includes a first main body unit. The second terminal plate includes a second main body unit. The second main body unit opposes the first main body unit. The third terminal plate includes a third main body unit. The third main body unit opposes the first main body unit and the second main body unit. The fourth terminal plate includes a fourth main body unit. The fourth main body unit opposes the third main body unit. A thickness of the third main body unit is thinner than a thickness of the first main body unit. A thickness of the fourth main body unit is thinner than a thickness of the second main body unit.

Abstract: According to an embodiment, a wiring board includes an insulating board including a heat transfer region made of silicon nitride and having a thickness in a range between 0.2 mm and 1 mm; and a wiring layer including a pad stacked on the heat transfer region and made of a metal material having a thickness of 1.5 mm or more.

Abstract: A semiconductor device includes a base plate, a semiconductor chip, and a first to a fourth terminal plates. The first terminal plate includes a first main body unit. The second terminal plate includes a second main body unit. The second main body unit opposes the first main body unit. The third terminal plate includes a third main body unit. The third main body unit opposes the first main body unit and the second main body unit. The fourth terminal plate includes a fourth main body unit. The fourth main body unit opposes the third main body unit. A thickness of the third main body unit is thinner than a thickness of the first main body unit. A thickness of the fourth main body unit is thinner than a thickness of the second main body unit.

Abstract: A semiconductor device includes a substrate joined to a base by a first junction material and a semiconductor element joined to the substrate by a second junction material. At least one of the first and second junction materials comprises tin, antimony, and cobalt. In some embodiments, the junction materials comprise cobalt having a weight percentage between 0.05 wt % and 0.2 wt %, antimony with a weight percentage between 1 wt % and 10 wt %, and the balance being substantially tin.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor element, an interconnection layer, and a bonding layer. The interconnection layer includes Cu. The bonding layer includes a first alloy that is an alloy of Cu and a first metal other than Cu between the semiconductor element and the interconnection layer. A melting point of the first alloy is higher than a melting point of the first metal.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor element and a metal film. The semiconductor element has a first surface and a second surface opposite to the first surface. The metal film is provided above the second surface of the semiconductor element. The metal film includes Cr.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor element, an interconnection layer, and a bonding layer. The interconnection layer includes Cu. The bonding layer includes a first alloy that is an alloy of Cu and a first metal other than Cu between the semiconductor element and the interconnection layer. A melting point of the first alloy is higher than a melting point of the first metal.

Abstract: According to one embodiment, in a method of testing a semiconductor device, the semiconductor device has a semiconductor element and a substrate which are bonded by bonding material including metal fine particles. Image data of a heat distribution in the semiconductor device are temporally acquired while heating the semiconductor device. A time change of a fractal dimension based on the image data is calculated. An inclination of the time change of the fractal dimension is calculated. The inclination and a reference inclination set in advance are compared. Whether or not the semiconductor device is good is determined.

Abstract: According to one embodiment, the semiconductor device in the embodiment has an assembly substrate, a semiconductor chip, and a jointing layer. The semiconductor chip is joined to the assembly substrate via the jointing layer. An intervening diffusion barrier layer may be interposed between the chip and jointing layer. The jointing layer is an alloy layer mainly made of any metal selected from Sn, Zn and In or an alloy of Sn, Zn and In, and any metal selected from Cu, Ni, Ag, Cr, Zr, Ti and V or an alloy of any metal selected from Cu, Ni, Ag, Cr, Zr, Ti and V and any metal selected from Sn, Zn and In, where the alloy has a higher melting temperature than that of Sn, Zn and In or an alloy of Sn, Zn and/or In.

Abstract: A method for fabricating a power semiconductor device that comprises a base substrate with a conductive layer on a surface of the base substrate and semiconductor components mounted on the base substrate includes forming a hardened layer on the surface of the conductive layer before mounting a semiconductor component on the base substrate. The forming of the hardened layer may optionally be performed using a peening process, for example, a shot peening process, a laser peening process, or an ultrasonic peening process. The conductive layer may comprise a metal such as, for example, aluminum or copper.

Abstract: According to one embodiment, the semiconductor device in the embodiment has an assembly substrate, a semiconductor chip, and a jointing layer. The semiconductor chip is joined to the assembly substrate via the jointing layer. An intervening diffusion barrier layer may be interposed between the chip and jointing layer. The jointing layer is an alloy layer mainly made of any metal selected from Sn, Zn and In or an alloy of Sn, Zn and In, and any metal selected from Cu, Ni, Ag, Cr, Zr, Ti and V or an alloy of any metal selected from Cu, Ni, Ag, Cr, Zr, Ti and V and any metal selected from Sn, Zn and In, where the alloy has a higher melting temperature than that of Sn, Zn and In or an alloy of Sn, Zn and/or In.

Abstract: According to one embodiment, a heatsink includes a base and heat radiation fins placed on one of surfaces of the base and arranged in parallel to each other with a submillimeter narrow pitch. Each of the multiple heat radiation fins has a submillimeter thickness, a length in a width direction of 60 mm or smaller, and a height of 40 mm or smaller. The heatsink assembly may be constituted by allaying a plurality of the heatsinks and thermally connecting each of the heatsinks to each other using a heat transport device.