Abstract: This description relates to an electrical power converter including a series connection of two transistors, and provides a technology for suppressing increase in electrical current flowing through the transistors when the two transistors are turned on at the same time for some defective reason. An electrical power converter disclosed herein includes a series connection of a first transistor and a second transistor. The electrical power converter includes a clamp circuit configured to inhibit an abnormal rise in gate voltage, which is provided in at least either the first transistor or the second transistor. The clamp circuit includes a diode and a capacitor. The diode has an anode connected with a gate of the transistor. The capacitor has one electrode connected with a cathode of the diode and the other electrode connected with an emitter of the transistor.