Abstract: A semiconductor memory device includes a gate electrode and a first and second semiconductor layer surrounding the gate electrode. A first electrode layer surrounds the gate electrode and contacts the first semiconductor layer. A second electrode layer surrounds the gate electrode and contacts the first and second semiconductor layers. The first semiconductor layer is between the first and second electrode layers. A third electrode layer surrounds the gate electrode and contacts the second semiconductor layer. The second semiconductor layer is between the second and third electrode layers. A first charge storage layer is between the gate electrode and the first semiconductor layer. A second charge storage layer is between the gate electrode and the second semiconductor layer.

Abstract: A switching element includes a first conductive layer, a second conductive layer, and a switching material layer provided between the first conductive layer and the second conductive layer and formed of an insulating material containing an additional element. The switching material layer includes a first interface region including a first interface between the first conductive layer and the switching material layer and a second interface region including a second interface between the second conductive layer and the switching material layer. A concentration of the additional element in the switching material layer has a first peak in the first interface region.

Abstract: A semiconductor device includes a first conductive layer extending along a first direction, a semiconductor layer extending along a second direction crossing the first direction, penetrating the first conductive layer, and including an oxide semiconductor, a first insulating layer between the first conductive layer and the semiconductor layer, a second conductive layer provided on one side of the semiconductor layer in the second direction and electrically connected thereto, a third conductive layer provided on the other side of the semiconductor layer in the second direction and electrically connected thereto, an electric conductor extending from the third conductive layer toward the second conductive layer along the semiconductor layer, and a charge storage film between the semiconductor layer and the electric conductor.

Abstract: A semiconductor device includes: an electronic circuit to receive a first signal and transmit a second signal; a power supply circuit to supply a power supply voltage to the electronic circuit; and a correction circuit to change a value of the power supply voltage to switch between a normal and a refresh operation mode. The electronic circuit includes: a first Pch transistor in which a potential of a first gate changes according to the first signal, and a potential of one of the first source and drain changes in response to the power supply voltage; and a first Nch transistor in which the second gate is electrically connected to the first gate, a potential of one of the second source and drain is equal to or lower than a ground potential, and another of the second source and drain is electrically connected to another of the first source and drain.

Abstract: According to an embodiment, a memory system includes a memory and a computation unit. Into the memory, data are written. The memory stores therein multiple check matrices. Each of the check matrices is associated with the number of errors in the written data. The computation unit is configured to perform a first error correction on the written data by selectively using, from among the check matrices, a check matrix associated with the number of errors recognized in the written data.

Abstract: An arithmetic control device according to an embodiment controls arithmetic operations using a memory chip. The memory chip includes a memory cell array and a controller. The memory cell array includes a plurality of memory cells. The controller is configured to control access to the memory cell array. The arithmetic control device includes a first writing unit and a first reading unit. The first writing unit requests the controller to write a first value to a second cell near a first cell of the memory cell array. The first reading unit requests the controller to read a second value from the first cell after the first value is written to the second cell.

Abstract: A photodetector according to an embodiment includes; at least one photodiode including: a first electrode; an n-type semiconductor layer disposed on the first electrode; a first p-type semiconductor layer disposed above the n-type semiconductor layer, the first p-type semiconductor layer including a first surface region and a second surface region; a second p-type semiconductor layer disposed in the first surface region of the first p-type semiconductor layer, the second p-type semiconductor layer having a higher p-type impurity concentration than the first p-type semiconductor layer; and a second electrode disposed on the second surface region of the first p-type semiconductor layer and on the second p-type semiconductor layer.

Abstract: An electrochemical sensor according to an embodiment includes a sensor unit, provided with a transistor including a first-conductivity type semiconductor layer, a second-conductivity type first conductive region provided in the semiconductor layer, a second-conductivity type second conductive region provided in the semiconductor layer, a first insulating film provided on the semi conductor layer between the first conductive region and the second conductive region, a charge storage film on the first insulating film, a second insulating film on the charge storage film, and a reference electrode, and a control circuit tor performing control based on a comparison result between a characteristic value measured by the sensor unit and a target value with respect to the characteristic value such that a predetermined voltage is applied between the semiconductor layer and the reference electrode.

Abstract: An electrochemical sensor according to an embodiment, includes a first insulating film, an electrode, a semiconductor layer provided between the first insulating film and the electrode, and a charge storage layer provided between the electrode and the semiconductor layer.

Abstract: According to an embodiment, a memory system includes first wiring lines; second wiring lines; third wiring lines; fourth wiring lines; and first and second storages. The first storage includes first memory cells arranged at intersections of the first wiring lines and the second wiring lines. Each of the third wiring lines is connected to any one of the first wiring lines. Each of the fourth wiring lines is pre-associated with a logical address specified by a host apparatus. The second storage includes second memory cells arranged at intersections of the third wiring lines and the fourth wiring lines. A resistance state of each of the second memory cells is set to a first resistance state or a second resistance state where a resistance value is lower than that in the first resistance state, according to a correspondence relationship between the logical address and the first wiring line.

Abstract: An arithmetic control device according to an embodiment controls arithmetic operations using a memory chip. The memory chip includes a memory cell array and a controller. The memory cell array includes a plurality of memory cells. The controller is configured to control access to the memory cell array. The arithmetic control device includes a first writing unit and a first reading unit. The first writing unit requests the controller to write a first value to a second cell near a first cell of the memory cell array. The first reading unit requests the controller to read a second value from the first cell after the first value is written to the second cell.

Abstract: According to an embodiment, a memory system includes first wiring lines; second wiring lines; third wiring lines; fourth wiring lines; and first and second storages. The first storage includes first memory cells arranged at intersections of the first wiring lines and the second wiring lines. Each of the third wiring lines is connected to any one of the first wiring lines. Each of the fourth wiring lines is pre-associated with a logical address specified by a host apparatus. The second storage includes second memory cells arranged at intersections of the third wiring lines and the fourth wiring lines. A resistance state of each of the second memory cells is set to a first resistance state or a second resistance state where a resistance value is lower than that in the first resistance state, according to a correspondence relationship between the logical address and the first wiring line.

Abstract: According to an embodiment, a memory system includes a memory and a computation unit. Into the memory, data are written. The memory stores therein multiple check matrices. Each of the check matrices is associated with the number of errors in the written data. The computation unit is configured to perform a first error correction on the written data by selectively using, from among the check matrices, a check matrix associated with the number of errors recognized in the written data.

Abstract: According to an embodiment, a semiconductor circuit includes a substrate, a tunnel oxide film, a charge storage film, a blocking layer, and plural nodes. The substrate is made of a semiconductor in which two diffusion layers each serving as either a source or a drain are formed. The tunnel oxide film is formed on a region of the substrate between the diffusion layers. The charge storage film is formed on the tunnel oxide layer and stores charge. The blocking layer is formed between the charge storage film and a gate electrode and has layers of a first oxide film, a nitride film and a second oxide film to have a thickness of 5 nm or larger but 15 nm or smaller. The nodes allow external application of voltages so that the source and the drain are reversed and allow detection a gate voltage, a drain current and a substrate current.

Abstract: According to an embodiment, a semiconductor circuit includes a substrate, a tunnel oxide film, a charge storage film, a blocking layer, and plural nodes. The substrate is made of a semiconductor in which two diffusion layers each serving as either a source or a drain are formed. The tunnel oxide film is formed on a region of the substrate between the diffusion layers. The charge storage film is formed on the tunnel oxide layer and stores charge. The blocking layer is formed between the charge storage film and a gate electrode and has layers of a first oxide film, a nitride film and a second oxide film to have a thickness of 5 nm or larger but 15 nm or smaller. The nodes allow external application of voltages so that the source and the drain are reversed and allow detection a gate voltage, a drain current and a substrate current.

Abstract: A nonvolatile programmable logic switch according to an embodiment includes: a memory cell transistor including: a first source region and a first drain region of a second conductivity type formed at a distance from each other in a first semiconductor region of a first conductivity type; a first insulating film, a charge storage film, a second insulating film, and a control gate stacked in this order and formed on the first semiconductor region between the first source region and the first drain region; a pass transistor including: a second source region and a second drain region of a second conductivity type formed at a distance from each other in a second semiconductor region of the first conductivity type; a third insulating film, a gate electrode stacked in this order and formed on the second semiconductor region between the second source region and the second drain region, the gate electrode being electrically connected to the first drain region; and an electrode for applying a substrate bias to the firs

Abstract: An electronic device includes a substrate, a first chip mounted on the substrate and having a first terminal, a second terminal, an input pad and a semiconductor time switch connected to the first terminal and the second terminal and configured to disconnect the first terminal and the second terminal upon lapse of a prescribed lifetime, the input pad being configured to set the prescribed lifetime, a second chip mounted on the substrate and incorporating an operational device having a third terminal connected to the first terminal and a fourth terminal serving as an input terminal for an external device, a first memory device mounted on the substrate, having a fifth terminal connected to the second terminal and storing information required for operating the operational device, and an encapsulater covering at least the input pad of the first chip.

Abstract: A nonvolatile programmable logic switch according to an embodiment includes: a memory cell transistor including: a first source region and a first drain region of a second conductivity type formed at a distance from each other in a first semiconductor region of a first conductivity type; a first insulating film, a charge storage film, a second insulating film, and a control gate stacked in this order and formed on the first semiconductor region between the first source region and the first drain region; a pass transistor including: a second source region and a second drain region of a second conductivity type formed at a distance from each other in a second semiconductor region of the first conductivity type; a third insulating film, a gate electrode stacked in this order and formed on the second semiconductor region between the second source region and the second drain region, the gate electrode being electrically connected to the first drain region; and an electrode for applying a substrate bias to the firs

Abstract: Basic logic gates are formed in a small area, and a highly integrated and microscopic structure is provided. In an nMOSFET and a pMOSFET, gate electrodes are formed facing each other and sandwiching a semiconductor region via gate insulting layers. Respective drain regions of the nMOSFET and the pMOSFET are connected to each other. A high potential is applied to a source region of the pMOSFET while an intermediate potential between the high and a low potential is applied to a source region of the nMOSFET. As a result, a NAND gate is provided. The intermediate potential between the high and the low potential is applied to the source region of the pMOSFET. The low potential is applied to the source region of the nMOSFET. As a result, a NOR gate is provided.

Abstract: A semiconductor circuit deterioration simulation method for a circuit including MOSFETs includes inserting a dynamic voltage source associated with a fluctuation in voltage/current characteristics into each gate terminal of a plurality of MOSFETs in series, calculating dynamic deterioration amounts of the plurality of MOSFETs by performing circuit simulation and calculating a dynamic deterioration amount, and repeating the above processing to perform the circuit deterioration simulation over the long term.