Patents by Inventor Kazuya Shuto

Kazuya Shuto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10136717
    Abstract: A waterproof enclosure for enclosing an electronic component includes an outer shell having a penetrating hole formed therethrough, a waterproof filter having air permeability and covering the penetrating hole, and a projecting part projecting from an outer surface of the outer shell and covering the penetrating hole, wherein the projecting part includes a plurality of vent holes connecting the penetrating hole to outside space, and wherein each of the vent holes is delimited by a sloping surface extending at an angle from the outer surface toward the penetrating hole.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: November 27, 2018
    Assignee: ALPS ELECTRIC CO., LTD.
    Inventor: Kazuya Shuto
  • Publication number: 20180055172
    Abstract: A waterproof enclosure for enclosing an electronic component includes an outer shell having a penetrating hole formed therethrough, a waterproof filter having air permeability and covering the penetrating hole, and a projecting part projecting from an outer surface of the outer shell and covering the penetrating hole, wherein the projecting part includes a plurality of vent holes connecting the penetrating hole to outside space, and wherein each of the vent holes is delimited by a sloping surface extending at an angle from the outer surface toward the penetrating hole.
    Type: Application
    Filed: June 26, 2017
    Publication date: March 1, 2018
    Inventor: Kazuya SHUTO
  • Patent number: 4143328
    Abstract: A digital phase lock loop circuit and method wherein the phase and the frequency of an output clock pulse of the circuit are made to instantaneously coincide with the phase and the frequency of an input clock pulse of the circuit. The digital phase lock loop circuit includes a fixed frequency generator circuit, an output frequency divider to which a standard clock pulse from the fixed frequency generator circuit is supplied via an inhibit gate, an output clock pulse frequency divider which divides the frequency of the output clock pulse from the output frequency divider, a phase comparator to which the input clock pulse and the divided clock pulse from the output clock pulse frequency divider are provided and an inhibit pulse generator to which the output of the phase comparator is supplied, so as to provide an inhibit pulse from the inhibit pulse generator to the inhibit gate.
    Type: Grant
    Filed: November 8, 1977
    Date of Patent: March 6, 1979
    Assignee: Fujitsu Limited
    Inventors: Shoichi Kurita, Yoshitaka Hiratsuka, Kazuya Shuto