Abstract: An information processing apparatus includes a processor, a plurality of memories, and a memory control circuitry coupled to the processor and the plurality of memories. The memory control circuitry controls access to the plurality of memories. The memory control circuitry includes a plurality of memory control circuits corresponding respectively to the plurality of memories, and a request distribution circuit that outputs the memory access request and a setting change request from the processor to one of the plurality of memory control circuits. Each of the plurality of memory control circuits includes an address translation control circuit that replaces bits of an address included in the memory access request based on allocation of bits changed based on the setting change request, and an access control circuit.

Abstract: An information processing apparatus includes a processor, a plurality of memories, and a memory control circuitry coupled to the processor and the plurality of memories. The memory control circuitry controls access to the plurality of memories. The memory control circuitry includes a plurality of memory control circuits corresponding respectively to the plurality of memories, and a request distribution circuit that outputs the memory access request and a setting change request from the processor to one of the plurality of memory control circuits. Each of the plurality of memory control circuits includes an address translation control circuit that replaces bits of an address included in the memory access request based on allocation of bits changed based on the setting change request, and an access control circuit.

Abstract: A memory controller includes: a determination part configured to determine a type of a DIMM having a different address line topology based on SPD; a slew rate setting part configured to set a slew rate of an address signal based on the type of the DIMM determined by the determination part; and a delay setting part configured to set a data delay amount when reading/writing data.

Abstract: An information processing apparatus includes a storage device that includes a plurality of storage areas, and a processor coupled to the storage device. The processor executes a process comprising: selecting a logical address identifying data stored in the storage device; acquiring a physical address associated with the selected logical address, from a conversion table storing therein the logical addresses and physical addresses identifying the storage areas in which the data is stored in association with each other; determining whether the stored data indicated by the acquired physical address is to be transferred; transferring the stored data to another storage area when it is determined that the data is to be transferred; and updating the physical address associated with the selected logical address in the conversion table to the physical address indicating the other storage area.

Abstract: To provide a technology of increasing the number of ranks of a memory module with a small change in architecture. A memory control device accessing a memory module having a plurality of ranks, includes an interface unit having selection signal lines via which to flow selection signals for selecting the ranks and address signal lines via which to flow address signals specifying addresses on the rank, and a control unit transmitting the signal for selecting the rank via part of the address signal line and via the selection signal line.

Abstract: A memory system connected to another apparatus via a data crossbar, has a first memory, a second memory that forms a dual configuration together with the first memory, a first memory controller that transmits or receives data to be written into the first memory or data read out from the first memory to or from the other apparatus, a second memory controller that transmits or receives data to be written into the second memory or data read out from the second memory to or from the other apparatus, and a system controller that instructs the first memory controller and the second memory controller to read out, from the first memory and the second memory, data requested to be read out by the other apparatus if the system controller detects that any one of the first data crossbar and the second data crossbar being not capable of transmitting or receiving data.

Abstract: A memory controller receives a read request and also issues a patrol request at a predetermined time interval so as to determine whether any error occurs in data stored in a DIMM. Furthermore, the memory controller generates a patrol address that is the subject of the subsequently issued patrol request. When the memory controller receives a read request, the memory controller compares the patrol address with the read address that is the subject of the received read request. When the read address matches the patrol address, the memory controller cancels the issuance of the subsequent patrol request.

Abstract: Two neighboring receiving units that receive a same signal notify each other of information representing that the signal has been received through the signal line, a process of correcting a transmission delay difference is performed according to a time difference between notification from the other receiving unit and its own signal reception, and selection of one of the neighboring receiving units and a receiving unit that has not performed a correction process with the one receiving unit among receiving units neighboring to the one receiving unit and a transmission delay difference correction process between the selected receiving units are sequentially performed. Thus, even when the number of processing target lanes increases, a transmission delay difference can be reliably absorbed and corrected while implementing an interconnection layout, a noise counter-measure, and a high-speed circuit.

Abstract: A memory controller includes: a determination part configured to determine a type of a DIMM having a different address line topology based on SPD; a slew rate setting part configured to set a slew rate of an address signal based on the type of the DIMM determined by the determination part; and a delay setting part configured to set a data delay amount when reading/writing data.

Abstract: A separation circuit separates a 32-bit dividend, (e.g., 1695) into 4-bit segments and outputs 9 separated dividends. The position of each dividend counted from the dividend having the lowest bit is i. A first output circuit concatenates at the end of a dividend, 0s of number equal to an integer multiple of 4 bits. Each calculation circuit outputs an 8-bit quotient, a numerical value created by the first output circuit divided by 3(=2n?1 and n=2), and outputs from a second output circuit, a first bit sequence that is the upper 4 bits of the 8-bit quotient, and a second bit sequence in which i sets of lower 4 bits of the 8-bit quotient are arranged. A quotient addition circuit outputs, as a quotient of 1695 divided by 3, the sum of values each including the first bit sequence at upper bits and the second bit sequence at lower bits.

Abstract: An information processing apparatus according to the present invention includes a controller for dividing data into a plurality of divided-data; a plurality of storage units for storing the plurality of divided-data, respectively; a plurality of storage controllers for writing the divided-data into the corresponding storage unit or reading out the divided-data from the respective storage units; a plurality of history storage units for storing histories of the operation of the corresponding storage controllers, respectively; an error detector for detecting an error in the divided-data; an error correction controller for controlling correction of the error; and a plurality of history controller for controlling update of the histories in the corresponding history storage units, respectively upon correction of the error.

Abstract: An information processing apparatus includes a data transmitting apparatus that transmits data of an N-bit width; a data receiving apparatus that receives the data of the N-bit width from the data transmitting apparatus; and a data bus of the N-bit width connecting the data transmitting apparatus and the data receiving apparatus. The data transmitting apparatus includes a first error-detection-code-attached data generation circuit, a second error-detection-code-attached data generation circuit, a first degeneration correspondence register, and a transmission-side selection circuit. The data receiving apparatus includes a first error checking circuit, a second error checking circuit, and a second degeneration correspondence register.

Abstract: A memory controller which is connected to a memory module having an ECC (Error Check and Correction) function and which controls access to the memory module, the memory controller, has an error detection unit configured to detect an error bit and a position of the error bit by reading, from the memory module, information on codes of the ECCs corresponding to a plurality of read data read from the memory module, a buffer configured to temporarily store the plurality of read data, and a determination unit configured to determine, when the plurality of read data stored in the buffer include a number of data in which a correctable error is detected by the error detection unit and error detection positions of the detected data are the same as each other, that a correctable error is included in a group of the plurality of read data.

Abstract: A memory system connected to another apparatus via a data crossbar, has a first memory, a second memory that forms a dual configuration together with the first memory, a first memory controller that transmits or receives data to be written into the first memory or data read out from the first memory to or from the other apparatus, a second memory controller that transmits or receives data to be written into the second memory or data read out from the second memory to or from the other apparatus, and a system controller that instructs the first memory controller and the second memory controller to read out, from the first memory and the second memory, data requested to be read out by the other apparatus if the system controller detects that any one of the first data crossbar and the second data crossbar being not capable of transmitting or receiving data.

Abstract: An information processing apparatus includes a data transmitting apparatus that transmits data of an N-bit width; a data receiving apparatus that receives the data of the N-bit width from the data transmitting apparatus; and a data bus of the N-bit width connecting the data transmitting apparatus and the data receiving apparatus. The data transmitting apparatus includes a first error-detection-code-attached data generation circuit, a second error-detection-code-attached data generation circuit, a first degeneration correspondence register, and a transmission-side selection circuit. The data receiving apparatus includes a first error checking circuit, a second error checking circuit, and a second degeneration correspondence register.

Abstract: An information processing apparatus according to the present invention includes a controller for dividing data into a plurality of divided-data; a plurality of storage units for storing the plurality of divided-data, respectively; a plurality of storage controllers for writing the divided-data into the corresponding storage unit or reading out the divided-data from the respective storage units; a plurality of history storage units for storing histories of the operation of the corresponding storage controllers, respectively; an error detector for detecting an error in the divided-data; an error correction controller for controlling correction of the error; and a plurality of history controller for controlling update of the histories in the corresponding history storage units, respectively upon correction of the error.

Abstract: To provide a technology of increasing the number of ranks of a memory module with a small change in architecture. A memory control device accessing a memory module having a plurality of ranks, includes an interface unit having selection signal lines via which to flow selection signals for selecting the ranks and address signal lines via which to flow address signals specifying addresses on the rank, and a control unit transmitting the signal for selecting the rank via part of the address signal line and via the selection signal line.