Patents by Inventor Kazuya Takakura

Kazuya Takakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for manufacturing tested apparatus and method for manufacturing system including tested apparatus
    Patent number: 9502314
    Abstract: Disclosed herein is a method for manufacturing a tested apparatus that includes forming a stacked structure that includes a plurality of first semiconductor chips stacked over a semiconductor wafer. The semiconductor wafer comprises a plurality of second semiconductor chips that are arranged in matrix of a plurality of rows and columns. Each of the first semiconductor chips is stacked over and electrically connected to a different one of the second semiconductor chips. The method further includes contacting a probe card to at least one of the first semiconductor chips to perform a first test operation on a corresponding one of the second semiconductor chips with an intervention of the at least one of the first semiconductor chips so that a plurality of tested apparatus each comprising a pair of first and second semiconductor chips stacked with each other is derived.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: November 22, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Tetsuji Takahashi, Toru Ishikawa, Kazuya Takakura
  • METHOD FOR MANUFACTURING TESTED APPARATUS AND METHOD FOR MANUFACTURING SYSTEM INCLUDING TESTED APPARATUS
    Publication number: 20150037914
    Abstract: Disclosed herein is a method for manufacturing a tested apparatus that includes forming a stacked structure that includes a plurality of first semiconductor chips stacked over a semiconductor wafer. The semiconductor wafer comprises a plurality of second semiconductor chips that are arranged in matrix of a plurality of rows and columns. Each of the first semiconductor chips is stacked over and electrically connected to a different one of the second semiconductor chips. The method further includes contacting a probe card to at least one of the first semiconductor chips to perform a first test operation on a corresponding one of the second semiconductor chips with an intervention of the at least one of the first semiconductor chips so that a plurality of tested apparatus each comprising a pair of first and second semiconductor chips stacked with each other is derived.
    Type: Application
    Filed: July 29, 2014
    Publication date: February 5, 2015
    Inventors: Tetsuji Takahashi, Toru Ishikawa, Kazuya Takakura