Patents by Inventor Kazuya Taniguchi

Kazuya Taniguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070109902
    Abstract: A semiconductor device for easily changing an operating voltage of an I/O circuit. The I/O circuit includes a first I/O cell, which operates with a first high-potential power supply, and a second I/O cell, which operates with a second high-potential power supply. The I/O circuit includes a control circuit for selectively activating the first and second I/O cells according to a voltage selection signal. In the I/O circuit, a signal having a voltage according to an operating voltage of the selected I/O cell is generated.
    Type: Application
    Filed: January 12, 2007
    Publication date: May 17, 2007
    Inventors: Kazuya Taniguchi, Toshiyuki Nishii, Hiromichi Mizuno
  • Publication number: 20070109901
    Abstract: A semiconductor device for easily changing an operating voltage of an I/O circuit. The I/O circuit includes a first I/O cell, which operates with a first high-potential power supply, and a second I/O cell, which operates with a second high-potential power supply. The I/O circuit includes a control circuit for selectively activating the first and second I/O cells according to a voltage selection signal. In the I/O circuit, a signal having a voltage according to an operating voltage of the selected I/O cell is generated.
    Type: Application
    Filed: January 12, 2007
    Publication date: May 17, 2007
    Inventors: Kazuya Taniguchi, Toshiyuki Nishii, Hiromichi Mizuno
  • Patent number: 7180812
    Abstract: A semiconductor device for easily changing an operating voltage of an I/O circuit. The I/O circuit includes a first I/O cell, which operates with a first high-potential power supply, and a second I/O cell, which operates with a second high-potential power supply. The I/O circuit includes a control circuit for selectively activating the first and second I/O cells according to a voltage selection signal. In the I/O circuit, a signal having a voltage according to an operating voltage of the selected I/O cell is generated.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: February 20, 2007
    Assignee: Fujitsu Limited
    Inventors: Kazuya Taniguchi, Toshiyuki Nishii, Hiromichi Mizuno
  • Publication number: 20060129720
    Abstract: There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls data transfer between a synchronous memory circuit and the asynchronous circuit, and a control method therefor, which are used in the buffer circuit and the control method therefor. A data buffer circuit that is interposed between an image processing system and a main system includes a one-port RAM, a control signal generating section, an subsequent cycle address generating section, and a first selector. The first selector selectively outputs the present cycle address to an address of the one-port RAM when an access to the one-port RAM is a write access, and selectively outputs the subsequent cycle address to the address of the one-port RAM when the access to the one-port RAM is a read access.
    Type: Application
    Filed: April 11, 2005
    Publication date: June 15, 2006
    Inventors: Kazuya Taniguchi, Toshiyuki Nishii, Hiromichi Mizuno, Tsutomu Terazawa
  • Publication number: 20060039206
    Abstract: A semiconductor device for easily changing an operating voltage of an I/O circuit. The I/O circuit includes a first I/O cell, which operates with a first high-potential power supply, and a second I/O cell, which operates with a second high-potential power supply. The I/O circuit includes a control circuit for selectively activating the first and second I/O cells according to a voltage selection signal. In the I/O circuit, a signal having a voltage according to an operating voltage of the selected I/O cell is generated.
    Type: Application
    Filed: November 29, 2004
    Publication date: February 23, 2006
    Inventors: Kazuya Taniguchi, Toshiyuki Nishii, Hiromichi Mizuno
  • Publication number: 20050213380
    Abstract: In a multiple power source semiconductor integrated circuit that is manufactured using a process which generates a large leakage current, supply of power to a function block that is not being used is stopped to reduce unnecessary power consumption. A multiple power source semiconductor integrated circuit (1) includes first to fourth function blocks (11) to (14) that are supplied with power from first to fourth power supply circuits (3) to (6), respectively, and a power supply control circuit (40) that controls supply of power by the first to fourth power supply circuits (3) to (6) under the control of a microcomputer as the first function block (11). The power supply control circuit (40) halts the supply of power to the first to fourth function blocks (11) to (14) when receiving prescribed data from the first function block (11), and restarts the supply of power when receiving a first or second interrupt signal (55) or (56) from outside.
    Type: Application
    Filed: April 4, 2003
    Publication date: September 29, 2005
    Inventors: Kazuya Taniguchi, Naoya Iguchi, Yasuhito Soma, Hisato Hayakawa
  • Patent number: 6895496
    Abstract: A microcontroller, connected to a memory which stores instructions and data, includes an instruction execution unit for reading instructions and data from the memory and processing the read instructions and a prefetch circuit unit that receives the instructions and data read from the memory and detects pseudo instructions included in the instructions and data. A pseudo instruction precedes a branch instruction and indicates the existence of the branch instruction and the branch to address. The prefetch circuit unit includes a prefetch buffer connected between the instruction execution unit and the memory for temporarily storing instructions and data being transferred from the memory to the instruction execution unit and a pseudo instruction buffer for temporarily storing instructions and data located at the address of the branch instruction which follows the pseudo instruction.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: May 17, 2005
    Assignee: Fujitsu Limited
    Inventors: Kazuya Taniguchi, Yukisato Miyazaki
  • Patent number: 6502179
    Abstract: A processor for performing calculations based on an instruction code, the number of bits of which is not an integer multiple of a byte. The instruction code is divided into higher order bits and lower order bits. The number of the lower order bits is an integer multiple of one byte. A memory stores the lower order bits in a lower order bit storage section and the higher order bits in a higher order bit storage section. The lower order bits and the corresponding higher order bits are read from the memory in the same cycle when generating the instruction code.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: December 31, 2002
    Assignee: Fujitsu Limited
    Inventors: Teruyoshi Kondo, Masayuki Takeshige, Sumitaka Hibino, Hayato Isobe, Yukisato Miyazaki, Kunihiro Ohara, Kazuya Taniguchi, Hiroshi Naritomi
  • Publication number: 20020023205
    Abstract: A processor for performing calculations based on an instruction code, the number of bits of which is not an integer multiple of a byte. The instruction code is divided into higher order bits and lower order bits. The number of the lower order bits is an integer multiple of one byte. A memory stores the lower order bits in a lower order bit storage section and the higher order bits in a higher order bit storage section. The lower order bits and the corresponding higher order bits are read from the memory in the same cycle when generating the instruction code.
    Type: Application
    Filed: January 25, 2001
    Publication date: February 21, 2002
    Inventors: Teruyoshi Kondo, Masayuki Takeshige, Sumitaka Hibino, Hayato Isobe, Yukisato Miyazaki, Kunihiro Ohara, Kazuya Taniguchi, Hiroshi Naritomi