Patents by Inventor Kazuya Togashi

Kazuya Togashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7576852
    Abstract: The surface of an epitaxial wafer is inspected using an optical scattering method. The intensities of light scattered with a narrow scattering angle and light scattered with a wide scattering angle reflected from laser light scatterers (LLS) on the wafer surface are detected. If the intensifies of narrowly and widely scattered lights are within a prescribed sizing range, it is judged whether the laser light scatterer is a particle or killer defect by deciding into which zone (410, 414, 418, 439) within the sizing range the PLS size based on the narrowly scattered light intensity and the PLS size based, on the widely scattered light intensity fall. If the intensity of the narrowly or widely scattered light exceeds the sizing range (417, 420, 421, 423, 424, 425), or if a plenty of laser light scatterers are continuous or concentrated (422), the laser light scatterers are judged to be killer defects.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: August 18, 2009
    Assignee: Sumco Tech XIV Corporation
    Inventors: Fumi Nabeshima, Kazuya Togashi, Hiroshi Jiken, Yoshinori Suenaga
  • Patent number: 7522290
    Abstract: A semiconductor wafer surface inspection apparatus detects LADs (Large Area Defects) which are flat and have low heights and differentiates them from particles. This inspection apparatus irradiates each point on the surface of a semiconductor wafer 200 with two parallel laser beams perpendicularly to the points while scanning the surface, and by measuring the phase difference between the two reflected beams, detects points 400 at which an upward inclination exists and points 402 at which a downward inclination exists on the surface of the wafer 200. Areas 404 in which pairs or sets of upward-inclination points 400 and downward-inclination points 402 exist within a prescribed range of mutual distances are inferred to be LADs.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: April 21, 2009
    Assignee: Sumco Tech XIV Corporation
    Inventors: Fumi Nabeshima, Kazuya Togashi
  • Publication number: 20090040512
    Abstract: The surface of an epitaxial wafer is inspected using an optical scattering method. The intensities of light scattered with a narrow scattering angle and light scattered with, a wide scattering angle reflected from laser light scatterers (LLS) on the wafer surface are detected. If the intensifies of narrowly and widely scattered lights are within a prescribed sizing range, it is judged whether the laser light scatterer is a particle or killer defect by deciding into which zone (410, 414, 418, 439) within the sizing range the PLS size based on the narrowly scattered light intensity and the PLS size based, on the widely scattered light intensity fall. If the intensity of the narrowly or widely scattered light exceeds the sizing range (417, 420, 421, 423, 424, 425), or if a plenty of laser light scatterers are continuous or concentrated (422), the laser light scatterers are judged to be killer defects.
    Type: Application
    Filed: September 14, 2006
    Publication date: February 12, 2009
    Applicant: Komatsu Electronic Metals Co., Ltd.
    Inventors: Fumi Nabeshima, Kazuya Togashi, Hiroshi Jiken, Yoshinori Suenaga
  • Publication number: 20070229815
    Abstract: A semiconductor wafer surface inspection apparatus detects LADs (Large Area Defects) which are flat and have low heights and differentiates them from particles. This inspection apparatus irradiates each point on the surface of a semiconductor wafer 200 with two parallel laser beams perpendicularly to the points while scanning the surface, and by measuring the phase difference between the two reflected beams, detects points 400 at which an upward inclination exists and points 402 at which a downward inclination exists on the surface of the wafer 200. Areas 404 in which pairs or sets of upward-inclination points 400 and downward-inclination points 402 exist within a prescribed range of mutual distances are inferred to be LADs.
    Type: Application
    Filed: June 1, 2005
    Publication date: October 4, 2007
    Applicant: Komatsu Electronic Metals Co., Ltd.
    Inventors: Fumi Nabeshima, Kazuya Togashi
  • Patent number: 7147710
    Abstract: There is described a method which enables stable manufacture of a high-quality, ultra-thin epitaxial silicon wafer, as well as an epitaxial silicon wafer capable of bearing shipment manufactured by the method. A method of manufacturing an epitaxial silicon wafer having an ultra-thin epitaxial film, by means of forming an epitaxial film on a silicon wafer after having annealed the silicon wafer, includes the steps of: sufficiently smoothing COPs formed in the surface of the silicon wafer by means of appropriately setting annealing conditions according to an size of COPs in the vicinity of a surface of the silicon wafer; and forming an epitaxial film through epitaxial growth.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: December 12, 2006
    Assignee: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Kazuya Togashi, Masayoshi Danbata, Kuniaki Arai, Kaori Matsumoto
  • Publication number: 20030068502
    Abstract: There is described a method which enables stable manufacture of a high-quality, ultra-thin epitaxial silicon wafer, as well as an epitaxial silicon wafer capable of bearing shipment manufactured by the method. A method of manufacturing an epitaxial silicon wafer having an ultra-thin epitaxial film, by means of forming an epitaxial film on a silicon wafer after having annealed the silicon wafer, includes the steps of: sufficiently smoothing COPs formed in the surface of the silicon wafer by means of appropriately setting annealing conditions according to an size of COPs in the vicinity of a surface of the silicon wafer; and forming an epitaxial film through epitaxial growth.
    Type: Application
    Filed: November 18, 2002
    Publication date: April 10, 2003
    Applicant: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Kazuya Togashi, Masayoshi Danbata, Kuniaki Arai, Kaori Matsumoto
  • Patent number: 4857270
    Abstract: A process for manufacturing a silicon-germanium alloy comprising introducing SiH.sub.4 gas, GeCl.sub.4 gas and P-type or N-type doping gas into a reaction vessel, heating a substrate up to a temperature not lower than 750.degree. C., and depositing a thickly-grown, bulky silicon-germanium alloy upon the substrate within the reaction vessel.
    Type: Grant
    Filed: April 20, 1988
    Date of Patent: August 15, 1989
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Shinji Maruya, Yoshifumi Yatsurugi, Kazuya Togashi