Abstract: In a noise shaping requantization circuit, a requantized output digital signal and an input digital signal are processed in an operational circuit whose output signal is requantized to provide the requantized output signal. The processing circuit can be configured in a variety of ways but has fixed limitations established for circuit parameters which determine the relationship between the output signal therefrom and the two input signals. By comparison with prior art noise shaping requantization circuits, a substantially better S/N ratio (assuming equal values of output signal resolution), or a substantially lower degree of output signal resolution (assuming equal values of S/N ratio) can be achieved, with stable operation.

Abstract: A PWM type D/A converter having a first PWM converter, a second PWM converter and an analog adder. The digital input signals are designated as odd and even numbered input signals and the reference timing points for outputting odd/even numbered input signal are designated as odd/even numbered reference timing points. The first PWM converter receive the digital input signal to output signal whose rising/falling timing point is set at the earlier/later timing, the larger the value of the odd/even numbered input signal relative to the odd/even numbered reference timing point and the pulse width is determined by the values of the odd numbered input signal and the next even numbered input signal.

Abstract: A clock generator for digital demodulators is disclosed wherein a voltage-controlled oscillator (19) generates clock pulses at controlled frequency and phase in response to error signals from a phase comparator (14) and a frequency comparator (12). The phase error signal represents a phase deviation of the clock from a window pulse which is generated in response to a predetermined transition between binary "1"s and binary "0"s of an input bit stream. The frequency comparator detects the frequency of the clock pulse and compares it with lower and upper limits of a predetermined range of frequency variations and generates a frequency control signal having different voltages depending on the result of the comparison.

Abstract: A clock generator for digital demodulators is disclosed wherein a voltage-controlled oscillator (19) generates clock pulses at controlled frequency and phase in response to error signals from a phase comparator (14) and a frequency comparator (12). The phase error signal represents a phase deviation of the clock from a window pulse which is generated in response to a predetermined transition between binary "1"s and binary "0"s of an input bit stream. The frequency comparator detects a synchronization code in the input bit stream to derive the frequency error signal by counting the number of clock pulses present in the period of the detected synchronization code.

Abstract: In a sample-and-hold circuit having two voltage amplifiers connected in series via a switch, which is arranged to perform on-off operations in accordance with a control signal, the noninverting input terminal of the second voltage amplifier of output side is grounded so that the switch can be used at an imaginal short point of the second voltage amplifier. As a result, a semiconductor switch having a simple construction may be used as the switch, while a switch drive circuit may also be simple. Furthermore, since great negative feedback effect can be attained during sampling mode, the sample-and-hold circuit is capable of operating with high accuracy. Additional switches may be employed for improving feedthrough characteristics, while means for preventing undesirable oscillation may be provided if necessary.

Abstract: A multiplier circuitry which multiplies an electrical signal by a multiplier signal comprises an oscillator which oscillates at a frequency having a predetermined relationship with respect to the multiplier signal, a first signal generator for producing an asymmetrical square wave signal in response to the output signal of the oscillator, a frequency divider for dividing the frequency of the asymmetrical square wave signal from the first signal generator by two to produce at least one asymmetrical square wave signal, and a second signal generator for multiplying an input electrical signal by the asymmetrical square wave signal and subsequently by a symmetrical square wave which is obtained from the asymmetrical square wave signal. The methods and apparatus for multiplying an electrical signal according to the present invention may be adapted to a phase comparator, modulator, demodulator and the like.

Abstract: A pilot signal cancelling signal is first combined with a composite stereo signal by a first predetermined ratio and thus a combined signal is fed to a stereo demodulator (3A) which produces a difference signal and an inverted difference signal, while the same cancelling signal is then combined with the composite stereo signal by a second predetermined ratio so that this combined signal will be used for producing left and right channel output signals by matrixing the difference signal and the inverted difference signal. At least three combiners (35, 39, 40) are utilized to effect the combination of the cancelling signal with the composite stereo signal.

Abstract: An automatic switching control circuit is responsive to a command signal as derived from manual tuning operation to change the operating modes of a feedback-controlled system such as automatic frequency control circuit, and includes a first impedance element, an inverting amplifier and a second impedance element in a series circuit between an input terminal to which an error signal from the feedback-controlled signal is applied and an output terminal from which a compensation signal is applied to a modulating element of the feedback-controlled system. A third impedance element is connected between the output terminal and a reference terminal. A switch is provided to establish a short circuit path between the input of the inverting amplifier and the output terminal. The voltage across the third impedance element automatically reduces to substantially zero voltage level in response to the presence of the short circuit path so that the feedback control is suspended.

Abstract: A feedback resistor is interposed between a reversing input terminal of an audio amplifier and at least one impedance circuit. The impedance circuit is connected to an output terminal of the amplifier to receive an amplified audio signal from the amplifier. The signal controlled in its frequency characteristic in the impedance circuit. A fraction of the signal is negatively fed back to the amplifier through a feedback resistor.