Abstract: It is an object of the present invention to simplify a multiplier so as to reduce the circuit scale of a digital filter which uses a large number of multipliers. Outputs of a Booth decoder 4 are stored in registers 5.sub.1 -5.sub.(n+1)/2 provided corresponding to partial product generating circuits 106.sub.1 -106.sub.(n+1)2. By providing control signals from the registers 5.sub.1 -5.sub.(n+1)/2 to the partial product generating circuits 106.sub.1 -106.sub.(n+1)/2, the Booth decoder 4 is made common. The number of Booth decoders which have conventionally been provided in a one-to-one correspondence with the partial product generating circuits can be reduced to one and the multiplier can be simplified.

Abstract: It is an object to obtain a multiplier circuit with reduced circuit scale or with reduced power consumption. Booth decoders (BD1-BD3) receive overlapping three bits of a 6-bit multiplier (Y) (Y0-Y5), respectively, and output partial product information groups (S1-S5) to partial product generating circuits (PP1-PP3) on the basis of the three bits of the multiplier (Y), respectively. Each partial product information is provided in a one-to-one correspondence for each kind of partial product. The partial product generating circuits (PP1-PP3) respectively receive the partial product information groups (S1-S5) from the respective Booth decoders (BD1-BD3) and a 8-bit multiplicand (X) (X0-X7), and output partial products (SM1-SM3) to a partial product adder circuit (ADD1). The partial product adder circuit (ADD1) adds the partial products (SM1-SM3) and outputs a multiplication result (XY) of the multiplier (Y) and the multiplicand (X).

Abstract: Dummy information of a third level, which is between first and second levels written in a plurality of memory cells, is written in a dummy memory cell from a source node through transistors. Thus, a potential difference is caused between a read bit line and a dummy read bit line in reading. A potential comparison circuit indicates the level of information read from any memory cell on the basis of the comparison result as to the potentials of the dummy read bit line and the read bit line. Thus, the read rate is increased, the read operation is stabilized and increase of the chip area is suppressed.

Abstract: y memory blocks are connected in series. A row select signal is output to each memory block from a row address pointer corresponding to a plurality of memory circuits in one memory block. Similarly, a column select signal is output to each memory block from a column address pointer corresponding to a plurality of memory circuits in one memory block. Therefore, the same row and column select signals are applied to each memory block, whereby data is sequentially input/output for every memory block. Thus, the circuit complexity of the row and column address pointers can be reduced.

Abstract: A sequential access memory employs a dynamic type row address pointer 2 as a row address pointer for selecting row selection lines of a memory cell array 1, and a static type column address pointer 3 as a column address pointer for selecting a column selection lines 5 of memory cell array 1.