Patents by Inventor Kazuya Yano

Kazuya Yano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960719
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: April 16, 2024
    Assignee: Kioxia Corporation
    Inventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
  • Publication number: 20240114799
    Abstract: A piezoelectric substrate according to the present disclosure includes: a base body; an electrode formed at the base body; and a piezoelectric layer formed at the electrode and containing potassium, sodium, and niobium. A value of IR2/IR1 obtained by dividing an integrated intensity IR2 at a peak 2 by an integrated intensity IR1 at a peak 1, when a surface of the piezoelectric layer is measured by Fourier transform infrared spectroscopy, is less than 0.086. Here, the peak 1 has a strongest area intensity among peaks detected at wavenumbers of 475 cm?1 to 700 cm?1, and the peak 2 has an area intensity that is a sum of area intensities of peaks detected at wavenumbers of 1200 cm?1 to 1645 cm?1.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 4, 2024
    Inventors: Yoshiki YANO, Koji OHASHI, Yasuaki HAMADA, Kazuya KITADA
  • Publication number: 20240111416
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 4, 2024
    Applicant: Kioxia Corporation
    Inventors: Kazuya KITSUNAI, Shinichi KANNO, Hirokuni YANO, Toshikatsu HIDA, Junji YANO
  • Patent number: 9707629
    Abstract: A cutting tool includes a portion made of a high hardness material. The portion includes a rake face, a flank face, and a cutting edge. The rake face is divided into a region A along the cutting edge and a region B excluding the region A of the rake face, a surface roughness of the region A is smaller than a surface roughness of the region B, and the region B is deepened with respect to a position of the region A.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: July 18, 2017
    Assignees: SUMITOMO ELECTRIC HARDMETAL CORP., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kazuya Yano, Yoshinori Tanigawa, Yoshikazu Yamashita, Hiroyuki Shimada, Kazuo Nakamae
  • Patent number: 9684014
    Abstract: A prober can suppress a decrease of a throughput in inspection of semiconductor devices on a substrate. The prober 10 includes a stage 11 having a horizontal mounting surface 11a that mounts thereon a wafer W on which semiconductor devices are formed; a probe card 16 provided to face the stage 11; three roller devices 26, each having a vertical rotational shaft, equally-spaced along a circumference of the mounted wafer W. Each roller device 26 is configured to rotate the wafer W on a horizontal plane while being in contact with a peripheral edge of the wafer W.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: June 20, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shuji Akiyama, Kazuya Yano, Isamu Inomata
  • Patent number: 9523711
    Abstract: A probe apparatus includes a card clamp unit detachably supporting a probe card; and a wafer mounting table adsorbing the semiconductor wafer and bringing electrodes on the semiconductor wafer into contact with the probes. In order to mount the semiconductor wafer including an annular portion protruding from a rear surface of an outer peripheral portion and a thin portion having a thickness smaller than the annular portion, the wafer mounting table includes a planar portion on which the thin portion is mounted; and a step-shaped portion which is formed at an edge of the planar portion and mounts the annular portion thereon. Multiple circular vacuum chuck grooves are concentrically formed in the planar portion, and at least some of the vacuum chuck grooves are connected to multiple vacuum paths through which vacuum evacuation is performed at multiple positions separated from each other by 90° or more along a circumferential direction.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: December 20, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazuya Yano, Eiji Hayashi, Munetoshi Nagasaka
  • Patent number: 9383389
    Abstract: A prober 10 including a probe card 16 having multiple probe needles 17 includes a needle-tip polishing unit 24, and the needle-tip polishing unit 24 includes a WAPP 28 to be contacted with needle tips and a supporting member 27 configured to support the WAPP 28. On a top surface of the WAPP 28, a wrapping sheet 29 is provided, and the WAPP 28 includes multiple recesses 31 formed on a bottom surface 30 thereof and the supporting member 27 includes multiple protrusions 33 formed on a ceiling surface 32 thereof. When the WAPP 28 is moved to a retreat position, the protrusions 33 are respectively inserted and fitted into the recesses 31, and when the WAPP 28 is moved to a contact position, top portions of the protrusions 33 are respectively brought into contact with portions on the bottom surface 30 where the recesses 31 are not formed.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: July 5, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazuya Yano, Shuji Akiyama
  • Patent number: 9261553
    Abstract: A probe apparatus of inspecting electrical characteristics of a power device having electrodes on both sides of a substrate at wafer level can reduce and uniformize a contact resistance between the electrode on a rear surface of the substrate and a mounting surface conductor of a chuck top. In the probe apparatus, an attracting device supports a semiconductor wafer W on the chuck top 12, and has many vertical fine holes in a pattern (diameter ? and pitch p) that satisfies the condition of ?<p?2?. For example, the diameter ? is about 0.25 mm, and the pitch p is about 0.5 mm.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: February 16, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Eiichi Shinohara, Munetoshi Nagasaka, Isamu Inomata, Kazuya Yano, Yoshiyasu Kato
  • Publication number: 20150226767
    Abstract: A prober can suppress a decrease of a throughput in inspection of semiconductor devices on a substrate. The prober 10 includes a stage 11 having a horizontal mounting surface 11a that mounts thereon a wafer W on which semiconductor devices are formed; a probe card 16 provided to face the stage 11; three roller devices 26, each having a vertical rotational shaft, equally-spaced along a circumference of the mounted wafer W. Each roller device 26 is configured to rotate the wafer W on a horizontal plane while being in contact with a peripheral edge of the wafer W.
    Type: Application
    Filed: February 11, 2015
    Publication date: August 13, 2015
    Inventors: Shuji Akiyama, Kazuya Yano, Isamu Inomata
  • Publication number: 20150204909
    Abstract: A prober 10 including a probe card 16 having multiple probe needles 17 includes a needle-tip polishing unit 24, and the needle-tip polishing unit 24 includes a WAPP 28 to be contacted with needle tips and a supporting member 27 configured to support the WAPP 28. On a top surface of the WAPP 28, a wrapping sheet 29 is provided, and the WAPP 28 includes multiple recesses 31 formed on a bottom surface 30 thereof and the supporting member 27 includes multiple protrusions 33 formed on a ceiling surface 32 thereof. When the WAPP 28 is moved to a retreat position, the protrusions 33 are respectively inserted and fitted into the recesses 31, and when the WAPP 28 is moved to a contact position, top portions of the protrusions 33 are respectively brought into contact with portions on the bottom surface 30 where the recesses 31 are not formed.
    Type: Application
    Filed: January 21, 2015
    Publication date: July 23, 2015
    Inventors: Kazuya Yano, Shuji Akiyama
  • Publication number: 20150145547
    Abstract: A probe apparatus includes a card clamp unit detachably supporting a probe card; and a wafer mounting table adsorbing the semiconductor wafer and bringing electrodes on the semiconductor wafer into contact with the probes. In order to mount the semiconductor wafer including an annular portion protruding from a rear surface of an outer peripheral portion and a thin portion having a thickness smaller than the annular portion, the wafer mounting table includes a planar portion on which the thin portion is mounted; and a step-shaped portion which is formed at an edge of the planar portion and mounts the annular portion thereon. Multiple circular vacuum chuck grooves are concentrically formed in the planar portion, and at least some of the vacuum chuck grooves are connected to multiple vacuum paths through which vacuum evacuation is performed at multiple positions separated from each other by 90° or more along a circumferential direction.
    Type: Application
    Filed: April 25, 2013
    Publication date: May 28, 2015
    Inventors: Kazuya Yano, Eiji Hayashi, Munetoshi Nagasaka
  • Patent number: D794691
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: August 15, 2017
    Assignee: SUMITOMO ELECTRIC HARDMETAL CORP.
    Inventor: Kazuya Yano
  • Patent number: D844034
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: March 26, 2019
    Assignee: SUMITOMO ELECTRIC HARDMETAL CORP.
    Inventor: Kazuya Yano
  • Patent number: D844683
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: April 2, 2019
    Assignee: SUMITOMO ELECTRIC HARDMETAL CORP.
    Inventor: Kazuya Yano
  • Patent number: D847231
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: April 30, 2019
    Assignee: SUMITOMO ELECTRIC HARDMETAL CORP.
    Inventors: Machiko Abe, Hiroyuki Shimada, Kazuya Yano
  • Patent number: D856387
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 13, 2019
    Assignee: SUMITOMO ELECTRIC HARDMETAL CORP.
    Inventors: Machiko Abe, Hiroyuki Shimada, Kazuya Yano
  • Patent number: D857069
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 20, 2019
    Assignee: SUMITOMO ELECTRIC HARDMETAL CORP.
    Inventors: Machiko Abe, Hiroyuki Shimada, Kazuya Yano
  • Patent number: D882653
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: April 28, 2020
    Assignee: Sumitomo Electric Hardmetal Corp.
    Inventors: Machiko Abe, Hiroyuki Shimada, Kazuya Yano
  • Patent number: D888786
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: June 30, 2020
    Assignee: Sumitomo Electric Hardmetal Corp.
    Inventors: Machiko Abe, Hiroyuki Shimada, Kazuya Yano
  • Patent number: D910093
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: February 9, 2021
    Assignee: Sumitomo Electric Hardmetal Corp.
    Inventors: Machiko Abe, Hiroyuki Shimada, Kazuya Yano