Patents by Inventor Kazuyasu Fujishima
Kazuyasu Fujishima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6859403Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss?, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss?.Type: GrantFiled: April 2, 2004Date of Patent: February 22, 2005Assignee: Renesas Technology Corp.Inventors: Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima, Masaki Tsukude
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Publication number: 20040184332Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.Type: ApplicationFiled: April 2, 2004Publication date: September 23, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima, Masaki Tsukude
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Publication number: 20020149973Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.Type: ApplicationFiled: June 7, 2002Publication date: October 17, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima, Masaki Tsukude
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Patent number: 6414883Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.Type: GrantFiled: May 21, 2001Date of Patent: July 2, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima, Masaki Tsukude
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Patent number: 6404056Abstract: On transistors P1, P2, N1 and N2 constituting an NAND gate, a interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line LL for connecting transistors P1, P2, N1 and N2 to each other is formed by the interconnection pattern W of metal having high melting point, signal lines SL and SL′ for signal input/output between the NAND gate and the outside are formed by aluminum interconnection pattern Al1, and power supply lines VL and VL′ for applying power supply potentials Vcc and Vss to the NAND gate are formed by the aluminum interconnection pattern Al2. As compared with the prior art in which the local line LL is formed by the aluminum interconnection pattern Al1, the degree of freedom in layout can be improved and the layout area can be reduced.Type: GrantFiled: May 18, 1999Date of Patent: June 11, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shigehiro Kuge, Kazutami Arimoto, Masaki Tsukude, Kazuyasu Fujishima
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Patent number: 6404691Abstract: A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.Type: GrantFiled: June 7, 1995Date of Patent: June 11, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura
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Publication number: 20010024383Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.Type: ApplicationFiled: May 21, 2001Publication date: September 27, 2001Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima, Masaki Tsukude
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Patent number: 6272055Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.Type: GrantFiled: October 9, 1998Date of Patent: August 7, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima, Masaki Tsukude
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Patent number: 6214664Abstract: In a semiconductor device and a method of manufacturing the same, an isolating and insulating film is provided at an end neighboring to a second impurity region with a groove extended to a semiconductor substrate. This removes a crystal defect existed at the end of the isolating and insulating film, and thus prevents leak of a current at this portion from a storage node. Consequently, provision of the groove at the edge portion of the isolating oxide film neighboring to the impurity region removes a crystal defect at this region, and thus eliminates a possibility of leak of a current.Type: GrantFiled: November 18, 1999Date of Patent: April 10, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroshi Kimura, Tadashi Nishimura, Takahiro Tsuruda, Kazutami Arimoto, Tadato Yamagata, Kazuyasu Fujishima
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Patent number: 6075732Abstract: A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.Type: GrantFiled: June 17, 1999Date of Patent: June 13, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tsukasa Ooishi, Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Kazuyasu Fujishima
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Patent number: 6069379Abstract: In a semiconductor device and a method of manufacturing the same, an isolating and insulating film is provided at an end neighboring to a second impurity region with a groove extended to a semiconductor substrate. This removes a crystal defect existed at the end of the isolating and insulating film, and thus prevents leak of a current at this portion from a storage node. Consequently, provision of the groove at the edge portion of the isolating oxide film neighboring to the impurity region removes a crystal defect at this region, and thus eliminates a possibility of leak of a current.Type: GrantFiled: November 6, 1997Date of Patent: May 30, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroshi Kimura, Tadashi Nishimura, Takahiro Tsuruda, Kazutami Arimoto, Tadato Yamagata, Kazuyasu Fujishima
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Patent number: 5982678Abstract: A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.Type: GrantFiled: June 26, 1997Date of Patent: November 9, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tsukasa Ooishi, Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Kazuyasu Fujishima
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Patent number: 5969420Abstract: On transistors P1, P2, N1 and N2 constituting an NAND gate, interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line LL for connecting transistors P1, P2, N1 and N2 to each other is formed by the interconnection pattern W of metal having high melting point, signal lines SL and SL' for signal input/output between the NAND gate and the outside are formed by aluminum interconnection pattern Al1, and power supply lines VL and VL' for applying power supply potentials Vcc and Vss to the NAND gate are formed by the aluminum interconnection pattern Al2. As compared with the prior art in which the local line LL is formed by the aluminum interconnection pattern Al1, the degree of freedom in layout can be improved and the layout area can be reduced.Type: GrantFiled: June 24, 1997Date of Patent: October 19, 1999Assignee: Mitsubushi Denki Kabushiki KaishaInventors: Shigehiro Kuge, Kazutami Arimoto, Masaki Tsukude, Kazuyasu Fujishima
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Patent number: 5943273Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.Type: GrantFiled: July 23, 1997Date of Patent: August 24, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima, Masaki Tsukude
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Patent number: 5894440Abstract: Each of divided bit line pairs is selectively connected to a sub-input/output line pair through transfer gates. A register is connected to the sub-input/output line pair. Data is transferred through the sub-input/output line pair between the register and a selected bit line pair. A sense amplifier is connected to each of the bit line pairs. Sense amplifiers are independently driven by separate sense amplifier activating signals. Therefore, even if data is transferred to the selected bit line pair from the register, fluctuations in potential on the bit line pair caused in such a case does not affect a sense amplifier activating signal connected to a non-selected bit line pair. As a result, data stored in the non-selected memory cell is prevented from being destroyed.Type: GrantFiled: January 31, 1994Date of Patent: April 13, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masaki Tsukude, Kazutami Arimoto, Kazuyasu Fujishima, Yoshio Matsuda, Tsukasa Ooishi
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Patent number: 5687123Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.Type: GrantFiled: September 30, 1994Date of Patent: November 11, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima, Masaki Tsukude
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Patent number: 5682343Abstract: Main bit lines MBL and ZMBL are disposed at opposite sides of a sense amplifier SA. Main bit lines MBL and ZMBL each are provided for paired sub-bit lines SBL1 and SBL2 (or SBL3 and SBL4). Sub-bit line pair SBL1 and SBL2 is connected to main bit line MBL via a block select switch T1. Sub-bit line pair SBL3 and SBL4 is connected to main bit line ZMBL via a block select switch T2. Since one main bit line is provided for two sub-bit lines, a pitch of the main bit lines is twice as large as a pitch of the sub-bit lines, so that conditions on the pitch of main bit lines are remarkably eased, which facilitates layout of elements.Type: GrantFiled: June 17, 1996Date of Patent: October 28, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shigeki Tomishima, Masaki Tsukude, Mikio Asakura, Kazuyasu Fujishima
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Patent number: 5588130Abstract: A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.Type: GrantFiled: August 1, 1994Date of Patent: December 24, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura
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Patent number: RE36027Abstract: In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of V.sub.CC -V.sub.th, while the I/O line pair of a memory array portion not to be accessed is precharged to the level of 1/2.multidot.V.sub.CC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.Type: GrantFiled: June 13, 1996Date of Patent: January 5, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazutami Arimoto, Kazuyasu Fujishima, Hideto Hidaka, Masaki Tsukude, Tsukasa Ohishi
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Patent number: RE36089Abstract: Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.Type: GrantFiled: May 23, 1996Date of Patent: February 9, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tsukasa Ooishi, Kazutami Arimoto, Hideto Hidaka, Masanori Hayashikoshi, Shinji Kawai, Mikio Asakura, Masaki Tsukude, Katsuhiro Suma, Shigeki Tomishima, Kazuyasu Fujishima