Abstract: A current detection circuit includes an N-type first transistor configured to supply a first current to an output terminal, an N-type second transistor that constitutes a current mirror circuit with the first transistor, a comparison circuit configured to output a detection result showing whether or not the first current is larger than a predetermined threshold based on a current flowing through the second transistor, a ground fault detection circuit configured to output a result detecting a ground fault of the output terminal, and a logical circuit configured to output a current detection signal showing whether or not the first current is an overcurrent based on the detection result of the comparison circuit and the ground fault detection result of the ground fault detection circuit.

Abstract: An amplifier circuit includes, a first transistor and a first resistor connected in series between a power supply voltage and an output terminal. A second transistor and a second resistor are connected in series between the output terminal and a ground reference voltage. There is a first operational amplifier and a second operational amplifier. A first detection current corresponding to a voltage drop across first resistor is generated. A second detection current corresponding to a voltage drop across the second resistor is generated. A first replication circuit subtracts the second detection current from the first detection current. A third resistor conducts the current obtained by subtracting the second detection current from the first detection current.

Abstract: An amplifier circuit includes, a first transistor and a first resistor connected in series between a power supply voltage and an output terminal. A second transistor and a second resistor are connected in series between the output terminal and a ground reference voltage. There is a first operational amplifier and a second operational amplifier. A first detection current corresponding to a voltage drop across first resistor is generated. A second detection current corresponding to a voltage drop across the second resistor is generated. A first replication circuit subtracts the second detection current from the first detection current. A third resistor conducts the current obtained by subtracting the second detection current from the first detection current.

Abstract: A current detection circuit includes an N-type first transistor configured to supply a first current to an output terminal, an N-type second transistor that constitutes a current mirror circuit with the first transistor, a comparison circuit configured to output a detection result showing whether or not the first current is larger than a predetermined threshold based on a current flowing through the second transistor, a ground fault detection circuit configured to output a result detecting a ground fault of the output terminal, and a logical circuit configured to output a current detection signal showing whether or not the first current is an overcurrent based on the detection result of the comparison circuit and the ground fault detection result of the ground fault detection circuit.

Abstract: A load modulation circuit of an embodiment has a first element, a switch element configured to connect the first element to an end portion of a coil, a first control section configured to control an operation of the switch element, and a second control section configured to control an amount of electric charges accumulated in the first element, and the second control section discharges the electric charges accumulated in the first element when the switch element is switched to off.

Abstract: A rectification circuit connected to a coil and a capacitor, includes, on each terminal side of the coil, a high-side transistor connected between a terminal of the coil and the capacitor, first and second low-side transistors connected in parallel between the terminal of the coil and a fixed potential, a comparator that causes the first low-side transistor to be turned on when a voltage of the terminal of the coil decreases to a first value and then turned off when the voltage increases to a second value that is higher than the first value and lower than the fixed potential, and a controller that causes the second low-side transistor to be turned off when the voltage decreases to a third value that is higher than the second value and lower than the fixed potential, and then turned off when the voltage increases to the third value.

Abstract: A load modulation circuit of an embodiment has a first element, a switch element configured to connect the first element to an end portion of a coil, a first control section configured to control an operation of the switch element, and a second control section configured to control an amount of electric charges accumulated in the first element, and the second control section discharges the electric charges accumulated in the first element when the switch element is switched to off.

Abstract: A DC-DC converter supplies an output voltage to a plurality of channels of a light emitting device array in common. A current driver has a plurality of driver units which drive the channels. Each of the driver units includes a drive transistor and a detector which detects an abnormality of a drive current. A logic unit generates digital data in response to a plurality of detection signals and supplies the same to a D/A converter. An analog reference voltage of the D/A converter is supplied to the DC-DC converter. The logic unit executes a calibration operation which determines digital data for setting the minimum output DC voltage at the normal operation of all the channels by sequential updating of the digital data.

Abstract: A DC-DC converter supplies an output voltage to a plurality of channels of a light emitting device array in common. A current driver has a plurality of driver units which drive the channels. Each of the driver units includes a drive transistor and a detector which detects an abnormality of a drive current. A logic unit generates digital data in response to a plurality of detection signals and supplies the same to a D/A converter. An analog reference voltage of the D/A converter is supplied to the DC-DC converter. The logic unit executes a calibration operation which determines digital data for setting the minimum output DC voltage at the normal operation of all the channels by sequential updating of the digital data.

Abstract: There is a need for preventing a MOS transistor from being destroyed due to an inrush current from an input terminal when a boost operation starts from a boost disabling state. During the boost operation, a third MOS transistor (M3) turns off and a fourth MOS transistor (M4) turns on to prevent a current leak from an output terminal (Vout) to an input terminal (Vin) due to a parasitic diode of a second MOS transistor (M2). In the boost disabling state, the third MOS transistor turns on and the fourth MOS transistor turns off to prevent a current leak from the input terminal to the output terminal due to the parasitic diode of the second MOS transistor. When the boost operation starts from the boost disabling state, an electrode toward the output terminal of the second MOS transistor is charged before changing a substrate bias state of this transistor. In this manner, an inrush current is prevented from flowing from the input terminal to the output terminal via the parasitic diode of the second MOS transistor.

Abstract: There is a need for preventing a MOS transistor from being destroyed due to an inrush current from an input terminal when a boost operation starts from a boost disabling state. During the boost operation, a third MOS transistor (M3) turns off and a fourth MOS transistor (M4) turns on to prevent a current leak from an output terminal (Vout) to an input terminal (Vin) due to a parasitic diode of a second MOS transistor (M2). In the boost disabling state, the third MOS transistor turns on and the fourth MOS transistor turns off to prevent a current leak from the input terminal to the output terminal due to the parasitic diode of the second MOS transistor. When the boost operation starts from the boost disabling state, an electrode toward the output terminal of the second MOS transistor is charged before changing a substrate bias state of this transistor. In this manner, an inrush current is prevented from flowing from the input terminal to the output terminal via the parasitic diode of the second MOS transistor.