Patents by Inventor Kazuyo Matsumoto

Kazuyo Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10381443
    Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kazuyo Matsumoto, Yasuo Kasagi, Satoshi Shimizu, Hiroyuki Ogawa, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
  • Patent number: 10224340
    Abstract: A planar material layer stack including a lower etch stop dielectric layer, a sacrificial semiconductor layer, and an upper etch stop dielectric layer is formed over a source semiconductor layer on a substrate. An alternating stack of insulating layers and spacer material layers is formed. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. An array of memory stack structures is formed. A source cavity is formed by removing the sacrificial semiconductor layer and portions of the memory films. Source strap structures are formed by a selective semiconductor deposition process on the vertical semiconductor channels and the source semiconductor layer. A dielectric fill material layer fills a remaining volume of the source cavity.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: March 5, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Tsuyoshi Hada, Satoshi Shimizu, Kazuyo Matsumoto
  • Publication number: 20180366486
    Abstract: A planar material layer stack including a lower etch stop dielectric layer, a sacrificial semiconductor layer, and an upper etch stop dielectric layer is formed over a source semiconductor layer on a substrate. An alternating stack of insulating layers and spacer material layers is formed. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. An array of memory stack structures is formed. A source cavity is formed by removing the sacrificial semiconductor layer and portions of the memory films. Source strap structures are formed by a selective semiconductor deposition process on the vertical semiconductor channels and the source semiconductor layer. A dielectric fill material layer fills a remaining volume of the source cavity.
    Type: Application
    Filed: June 19, 2017
    Publication date: December 20, 2018
    Inventors: Tsuyoshi HADA, Satoshi SHIMIZU, Kazuyo MATSUMOTO
  • Publication number: 20180261671
    Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.
    Type: Application
    Filed: May 10, 2018
    Publication date: September 13, 2018
    Inventors: Kazuyo Matsumoto, Yasuo Kasagi, Satoshi Shimizu, Hiroyuki Ogawa, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
  • Patent number: 10020363
    Abstract: Sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions. A backside trench can be formed through the vertically alternating stack employing the sacrificial semiconductor line as an etch stop structure. Source strap material portions providing lateral electrical contact to semiconductor channels of the memory stack structures can be formed by replacement of sacrificial semiconductor material portions and the sacrificial semiconductor line with source strap material portions. Structural-reinforcement portions may be employed to provide structural stability during the replacement process.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: July 10, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroyuki Ogawa, Yasuo Kasagi, Satoshi Shimizu, Kazuyo Matsumoto, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
  • Patent number: 9985098
    Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: May 29, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kazuyo Matsumoto, Yasuo Kasagi, Satoshi Shimizu, Hiroyuki Ogawa, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
  • Publication number: 20180122905
    Abstract: Sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions. A backside trench can be formed through the vertically alternating stack employing the sacrificial semiconductor line as an etch stop structure. Source strap material portions providing lateral electrical contact to semiconductor channels of the memory stack structures can be formed by replacement of sacrificial semiconductor material portions and the sacrificial semiconductor line with source strap material portions. Structural-reinforcement portions may be employed to provide structural stability during the replacement process.
    Type: Application
    Filed: March 14, 2017
    Publication date: May 3, 2018
    Inventors: Hiroyuki Ogawa, Yasuo Kasagi, Satoshi Shimizu, Kazuyo Matsumoto, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
  • Publication number: 20180122904
    Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.
    Type: Application
    Filed: March 14, 2017
    Publication date: May 3, 2018
    Inventors: Kazuyo Matsumoto, Yasuo Kasagi, Satoshi Shimizu, Hiroyuki Ogawa, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
  • Patent number: 4729641
    Abstract: A functional optical element comprises a first optical member, a second optical member provided in contact with said first optical member, the interface between said first optical member and said second optical member being non-flat planar, a means for changing the refractive index of said second optical member, said means for changing refractive index being capable of creating selectively a first state in which said first optical member and said second optical member have an equal refractive index and a second state in which said first optical member and said second optical member have different refractive indices by changing the refractive index of said second optical member.
    Type: Grant
    Filed: April 30, 1987
    Date of Patent: March 8, 1988
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuhiko Matsuoka, Kazuo Minoura, Masayuki Usui, Yukuo Nishimura, Takeshi Baba, Atsushi Someya, Yuko Suga, Kazuyo Matsumoto