Patents by Inventor Kazuyo Nishikawa
Kazuyo Nishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8935461Abstract: A memory includes a storage element which stores the number of times of application of a rewrite voltage pulse into a memory array, and a required-time output unit which outputs data representing a required time for a rewrite operation based on the number of times of application stored in the storage element.Type: GrantFiled: January 14, 2013Date of Patent: January 13, 2015Assignee: Panasonic CorporationInventors: Kazuyo Nishikawa, Shuuhei Noichi, Makoto Arita, Junichi Katou, Asako Miyoshi
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Publication number: 20120002485Abstract: In a semiconductor memory circuit, a write voltage generation circuit receives an output voltage of a voltage boosting circuit to generate a write voltage to a memory cell. When the write voltage is low, a number-of-bits adjustment circuit increases the number of write bits of memory cells before write operation is performed. On the other hand, when the write voltage to a memory cell is high, the number-of-bits adjustment circuit decreases the number of write bits of memory cells before write operation is performed. The area and write time of the voltage boosting circuit can be reduced while the current supply capability of the voltage boosting circuit is efficiently used.Type: ApplicationFiled: September 15, 2011Publication date: January 5, 2012Applicant: PANASONIC CORPORATIONInventors: Hitoshi Suwa, Takafumi Maruyama, Takashi Ono, Tadashi Nitta, Kazuyo Nishikawa, Masahiro Ueminami
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Patent number: 7957193Abstract: There are provided a first nonvolatile memory array including a plurality of nonvolatile memory elements which require an erase operation before a write operation, and a second nonvolatile memory array including a plurality of overwritable nonvolatile memory elements. A request to rewrite data is received by a control circuit. The control circuit writes data to be rewritten to the second nonvolatile memory array when the capacity of the data to be rewritten is not more than that of the second nonvolatile memory array.Type: GrantFiled: February 26, 2009Date of Patent: June 7, 2011Assignee: Panasonic CorporationInventors: Kunisato Yamaoka, Kazuyo Nishikawa
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Patent number: 7782707Abstract: A semiconductor memory device comprises an address terminal through which an address for reading out stored data in a memory array is input, a clock input terminal through which an input clock is input, a data output terminal through which data read out from the memory array in accordance with the address is output, and a clock output terminal through which an output clock synchronous with the input clock is output. The clock output terminal invariably outputs one of a first voltage and a second voltage. Only when valid data is output from the data output terminal, the clock output terminal causes an output voltage to go from the first voltage to the second voltage or from one voltage to the other voltage.Type: GrantFiled: March 30, 2007Date of Patent: August 24, 2010Assignee: Panasonic CorporationInventors: Kazuyo Nishikawa, Masahiro Ueminami, Tadashi Nitta
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Publication number: 20100031001Abstract: In a serial memory device which performs reception and transmission of command, address, and data via serial communication with a host controller, a base address holding circuit holds a base address which serves as a base for effective address calculation. An address operation circuit calculates an effective address based on the base address and an address input from the host controller.Type: ApplicationFiled: June 18, 2009Publication date: February 4, 2010Inventors: Masahiro Ueminami, Kazuyo Nishikawa, Masahiro Kuramochi, Tadashi Nitta, Toshiki Mori
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Publication number: 20090296479Abstract: There are provided a first nonvolatile memory array including a plurality of nonvolatile memory elements which require an erase operation before a write operation, and a second nonvolatile memory array including a plurality of overwritable nonvolatile memory elements. A request to rewrite data is received by a control circuit. The control circuit writes data to be rewritten to the second nonvolatile memory array when the capacity of the data to be rewritten is not more than that of the second nonvolatile memory array.Type: ApplicationFiled: February 26, 2009Publication date: December 3, 2009Inventors: Kunisato Yamaoka, Kazuyo Nishikawa
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Patent number: 7522465Abstract: A semiconductor memory device includes: a power supply circuit for outputting a power supply voltage used for reading out data; and a power supply circuit status determination circuit for determining whether an operation status of the power supply circuit is such that data can be read out normally. The output of readout data is suppressed while it is determined by the power supply circuit status determination circuit that the operation status is such that data cannot be read out normally.Type: GrantFiled: March 1, 2007Date of Patent: April 21, 2009Assignee: Panasonic CorporationInventors: Tadashi Nitta, Kazuyo Nishikawa, Masahiro Ueminami
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Publication number: 20090080269Abstract: A semiconductor memory device comprises an address terminal through which an address for reading out stored data in a memory array is input, a clock input terminal through which an input clock is input, a data output terminal through which data read out from the memory array in accordance with the address is output, and a clock output terminal through which an output clock synchronous with the input clock is output. The clock output terminal invariably outputs one of a first voltage and a second voltage. Only when valid data is output from the data output terminal, the clock output terminal causes an output voltage to go from the first voltage to the second voltage or from one voltage to the other voltage.Type: ApplicationFiled: March 30, 2007Publication date: March 26, 2009Inventors: Kazuyo Nishikawa, Masahiro Ueminami, Tadashi Nitta
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Patent number: 7450461Abstract: In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a data-related circuit, an address-related circuit and a control-related circuit. These memory arrays however share a data terminal, an address terminal and a control terminal for chip external connection. A data, address and control signals are distributed to the memory arrays via three MUX of signal selection circuits controlled with an array selection signal (clock). A signal is supplied to one memory array at rising timing of the clock while a signal is supplied to another memory array at falling timing of the clock. Thus, in memory integration of placing a plurality of memory arrays on one chip, independent operation for each memory array is attained, and no bus arbitration between CPUs is necessary.Type: GrantFiled: October 5, 2006Date of Patent: November 11, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hisakazu Kotani, Motonobu Nishimura, Kazuyo Nishikawa, Masahiro Ueminami
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Publication number: 20070274148Abstract: A semiconductor memory device includes: a power supply circuit for outputting a power supply voltage used for reading out data; and a power supply circuit status determination circuit for determining whether an operation status of the power supply circuit is such that data can be read out normally. The output of readout data is suppressed while it is determined by the power supply circuit status determination circuit that the operation status is such that data cannot be read out normally.Type: ApplicationFiled: March 1, 2007Publication date: November 29, 2007Inventors: Tadashi Nitta, Kazuyo Nishikawa, Masahiro Ueminami
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Patent number: 7251717Abstract: While a plurality of physical address memories are provided with respect to one logical address of a non-volatile memory device, an empty physical address memory contained in the plural physical address memories is searched with respect to a writing operation for one logical address, and then, data is written in this empty physical address memory. With respect to a reading operation for one logical address, such a physical address memory to which data has been written at last is searched, and the storage content of this memory is read out. As a result, the data rewriting operation to a non-volatile memory can be carried out with employment of the simple circuit arrangement with respect to one logical address, while an erasing operation is not performed, and an area of a memory device is not increased but also a total number of data rewriting operation is not limited to a number defined in a specification of the memory device.Type: GrantFiled: June 9, 2004Date of Patent: July 31, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazuyo Nishikawa, Motonobu Nishimura
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Publication number: 20070081398Abstract: In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a data-related circuit, an address-related circuit and a control-related circuit. These memory arrays however share a data terminal, an address terminal and a control terminal for chip external connection. A data, address and control signals are distributed to the memory arrays via three MUX of signal selection circuits controlled with an array selection signal (clock). A signal is supplied to one memory array at rising timing of the clock while a signal is supplied to another memory array at falling timing of the clock. Thus, in memory integration of placing a plurality of memory arrays on one chip, independent operation for each memory array is attained, and no bus arbitration between CPUs is necessary.Type: ApplicationFiled: October 5, 2006Publication date: April 12, 2007Inventors: Hisakazu Kotani, Motonobu Nishimura, Kazuyo Nishikawa, Masahiro Ueminami
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Publication number: 20040255092Abstract: While a plurality of physical address memories are provided with respect to one logical address of a non-volatile memory device, an empty physical address memory contained in the plural physical address memories is searched with respect to a writing operation for one logical address, and then, data is written in this empty physical address memory. With respect to a reading operation for one logical address, such a physical address memory to which data has been written at last is searched, and the storage content of this memory is read out. As a result, the data rewriting operation to a non-volatile memory can be carried out with employment of the simple circuit arrangement with respect to one logical address, while an erasing operation is not performed, and an area of a memory device is not increased but also a total number of data rewriting operation is not limited to a number defined in a specification of the memory device.Type: ApplicationFiled: June 9, 2004Publication date: December 16, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kazuyo Nishikawa, Motonobu Nishimura