Patents by Inventor Kazuyoshi Amami

Kazuyoshi Amami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6818461
    Abstract: A mounting structure is formed by flip-chip mounting a semiconductor device onto a substrate. An electrical connecting portion of the semiconductor device is connected to an electrical connecting portion of the substrate by means of an electrically conductive adhesive. A region of the semiconductor device which is not involved in electrical connection is bonded to a region of the substrate which is not involved in electrical connection by means of an adhesive. A test of electrical properties is performed on the semiconductor device and the substrate which are connected to each other. If it is determined that the electrical properties are poor in the test, the semiconductor device is separated from the substrate after heating a bonding place of the adhesive up to a temperature higher than a glass transition point or a melting point of the adhesive. If it is determined that the electrical properties are good in the test, the semiconductor device and the substrate are sealed by means of a sealing resin.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: November 16, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuyoshi Amami, Tsukasa Shiraishi, Yoshihiro Bessho
  • Publication number: 20040212075
    Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.
    Type: Application
    Filed: May 20, 2004
    Publication date: October 28, 2004
    Inventors: Tsukasa Shiraishi, Tsutomu Mitani, Kazuyoshi Amami, Yoshihiro Bessho
  • Patent number: 6756663
    Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: June 29, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsukasa Shiraishi, Tsutomu Mitani, Kazuyoshi Amami, Yoshihiro Bessho
  • Patent number: 6723251
    Abstract: A method for planarizing a circuit board, has a step of fixing a circuit board having wiring layers on both sides to a board having a flat surface through an adhesive layer, wherein said circuit board is pressed from above by a flat member on fixing thereof.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: April 20, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Minehiro Itagaki, Yoshihiro Tomuro, Satoru Yuhaku, Kazuyoshi Amami
  • Patent number: 6703262
    Abstract: A method for planarizing a circuit board, has a step of fixing a circuit board having wiring layers on both sides to a board having a flat surface through an adhesive layer, wherein said circuit board is pressed from above by a flat member on fixing thereof.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: March 9, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Minehiro Itagaki, Yoshihiro Tomuro, Satoru Yuhaku, Kazuyoshi Amami
  • Publication number: 20030094685
    Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.
    Type: Application
    Filed: January 8, 2003
    Publication date: May 22, 2003
    Inventors: Tsukasa Shiraishi, Tsutomu Mitani, Kazuyoshi Amami, Yoshihiro Bessho
  • Publication number: 20030092327
    Abstract: A method for planarizing a circuit board, has a step of fixing a circuit board having wiring layers on both sides to a board having a flat surface through an adhesive layer, wherein said circuit board is pressed from above by a flat member on fixing thereof.
    Type: Application
    Filed: December 18, 2002
    Publication date: May 15, 2003
    Inventors: Minehiro Itagaki, Yoshihiro Tomuro, Satoru Yuhaku, Kazuyoshi Amami
  • Patent number: 6525414
    Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: February 25, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsukasa Shiraishi, Tsutomu Mitani, Kazuyoshi Amami, Yoshihiro Bessho
  • Patent number: 6468448
    Abstract: A pH adjusting agent is added to a conductive adhesive to prevent the dissolution of a conductive particle to improve the reliability of a mounting structure, wherein when a pH environment is produced in which the conductive particle is easy to dissolve in the surrounding of the conductive adhesive, the pH adjusting agent can change the pH environment to a pH environment in which the conductive particle is resistant to dissolving.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: October 22, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuyoshi Amami, Emiko Igaki, Minehiro Itagaki
  • Patent number: 6429382
    Abstract: For the reliability in insulation and against sulfurization, the mounting structure of the invention includes an electric structure, and an electrically conductive adhesive layer including an electrically conductive filler disposed on the electric structure, and at least a portion of surface of the electrically conductive filler is exposed to an external environment, and an elution preventive film is disposed on at least a portion of the exposed surface. Further, an electrically conductive adhesive of this invention includes the electrically conductive filler, and an elution preventive film is disposed on the entire surface of the electrically conductive filler.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: August 6, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuyoshi Amami, Hiroaki Takezawa, Tsukasa Shiraishi, Yoshihiro Bessho
  • Publication number: 20020072151
    Abstract: A mounting structure is formed by flip-chip mounting a semiconductor device onto a substrate. An electrical connecting portion of the semiconductor device is connected to an electrical connecting portion of the substrate by means of an electrically conductive adhesive. A region of the semiconductor device which is not involved in electrical connection is bonded to a region of the substrate which is not involved in electrical connection by means of an adhesive. A test of electrical properties is performed on the semiconductor device and the substrate which are connected to each other. If it is determined that the electrical properties are poor in the test, the semiconductor device is separated from the substrate after heating a bonding place of the adhesive up to a temperature higher than a glass transition point or a melting point of the adhesive. If it is determined that the electrical properties are good in the test, the semiconductor device and the substrate are sealed by means of a sealing resin.
    Type: Application
    Filed: February 5, 2002
    Publication date: June 13, 2002
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Kazuyoshi Amami, Tsukasa Shiraishi, Yoshihiro Bessho
  • Publication number: 20010029066
    Abstract: A method for planarizing a circuit board, has a step of fixing a circuit board having wiring layers on both sides to a board having a flat surface through an adhesive layer, wherein said circuit board is pressed from above by a flat member on fixing thereof.
    Type: Application
    Filed: November 19, 1998
    Publication date: October 11, 2001
    Inventors: MINEHIRO ITAGAKI, YOSHIHIRO TOMURO, SATORU YUHAKU, KAZUYOSHI AMAMI
  • Publication number: 20010002727
    Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.
    Type: Application
    Filed: November 29, 2000
    Publication date: June 7, 2001
    Inventors: Tsukasa Shiraishi, Tsutomu Mitani, Kazuyoshi Amami, Yoshihiro Bessho
  • Patent number: 5364253
    Abstract: A magnetic circuit component molding device for integrally molding a compound a center yoke with a ring-shaped magnet includes top and bottom press vertically arranged at opposed positions. A ring-shaped magnet is place on a bottom die between top and bottom press. The top and bottom press compress the compound against the ring-shaped magnet ring with a vertical pressure. A holder unit, separated in plural segments, having tapered outer circumferences is provided around the ring-shaped. A holder presser having a tapered inner circumference is mounted on the holder unit as tapered portions thereof are engaged together. A portion of the vertical pressure, when the top press compresses the compound, is transferred by springs 10 to the holder presser, and is amplified by the tapered portions and applied to the outer circumference surface of the ring-shaped magnet by the holder unit.
    Type: Grant
    Filed: May 14, 1993
    Date of Patent: November 15, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Kojima, Kazuyoshi Amami, Hiroshi Ueda, Shizuo Furuyama, Yoshihiro Hara, Kyoichi Hasegawa, Tadashi Kawamata