Patents by Inventor Kazuyoshi Arimura
Kazuyoshi Arimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9418812Abstract: An electric fuse includes a conductive material formed on a top surface of an insulating material. The conductive material includes a wiring portion, and first and second terminal portions arranged in two ends of the wiring portion so that the wiring portion is located between the first and second terminal portions. The first terminal portion, the wiring portion, and the second terminal portion are lined up in a first direction. The first and second terminal portions each have a width larger than a width of the wiring portion in a second direction perpendicular to the first direction. The electric fuse includes a film including an opening which exposes a region between the first terminal portion and the second terminal portion. The film is formed above at least a part of the wiring portion and has a tensile stress.Type: GrantFiled: January 14, 2013Date of Patent: August 16, 2016Assignee: SOCIONEXT INC.Inventors: Kazuyoshi Arimura, Akihiko Ono, Masashi Ishida
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Patent number: 9167647Abstract: A control circuit comprises a power supply unit configured to generate a voltage to be supplied to a load by turning on and off a first switch in response to a drive signal and control a drive current of the load by turning on and off a second switch in response to a control signal, a first controller configured to perform a first PWM control of the drive signal, based on a measurement value of the drive current, a second controller configured to perform a second PWM control of the control signal, based on an external signal, and a synchronous controller configured to synchronize an on-period of one period of the control signal to he a multiple of one period of the drive signal. Further, in the control circuit, during the on-period of the control signal, an inductor current for generating the drive current is cut off for a portion of every period of the drive signal.Type: GrantFiled: June 26, 2014Date of Patent: October 20, 2015Assignee: Cypress Semiconductor CorporationInventors: Koji Takekawa, Kazuyoshi Arimura
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Patent number: 8878336Abstract: A fuse includes a first conductor, an insulating film on the first conductor, a second conductor on the insulating film, a first plug coupled to the first conductor, a second plug and a third plug each coupled to the second conductor, and a cover film formed on the second conductor and having tensile strength.Type: GrantFiled: August 21, 2012Date of Patent: November 4, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Makoto Yasuda, Kazuyoshi Arimura, Yoshiharu Kato
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Publication number: 20130049165Abstract: A fuse includes a first conductor, an insulating film on the first conductor, a second conductor on the insulating film, a first plug coupled to the first conductor, a second plug and a third plug each coupled to the second conductor, and a cover film formed on the second conductor and having tensile strength.Type: ApplicationFiled: August 21, 2012Publication date: February 28, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Makoto Yasuda, Kazuyoshi Arimura, Yoshiharu Kato
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Patent number: 7546095Abstract: It is intended to provide a frequency multiplier capable of switching as appropriate among frequency signals having frequencies obtained by multiplying prescribed multiplication numbers with low current consumption and a simple circuit configuration in effectively utilizing frequencies in radio communication equipment. The base terminals of an input differential pair are biased by respective voltage sources, and an input frequency signal is input to one of the base terminals. The differential output terminals are connected to the base terminals of next-stage buffer circuit transistors, and their emitter terminals are connected to respective diodes. A full-wave-rectified signal, which is obtained at the connecting point of the cathode terminals of the diodes, is input to a comparison differential pair, which produces an output frequency signal by comparing the full-wave-rectified signal with a reference voltage.Type: GrantFiled: February 5, 2002Date of Patent: June 9, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Kazuyoshi Arimura
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Patent number: 7116258Abstract: A reference voltage generating circuit generates a reference voltage Vref. An A/D converting circuit compares an analog input voltage Vin with the reference voltage Vref to convert the analog input voltage Vin to a digital output value Dout. A measured value storing circuit stores a measured value of the reference voltage Vref in advance and outputs the stored measured value. A user of an A/D converter corrects the digital output value Dout from the A/D converting circuit by use of the measured value of the reference voltage Vref outputted from the measured value storing circuit, thereby obtaining a digital value representing the analog input voltage Vin accurately irrespective of the accuracy of the reference voltage Vref.Type: GrantFiled: March 24, 2006Date of Patent: October 3, 2006Assignee: Fujitsu LimitedInventors: Kazuyoshi Arimura, Atsushi Hayakawa, Hidekiyo Ozawa
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Publication number: 20060176204Abstract: A reference voltage generating circuit generates a reference voltage Vref. An A/D converting circuit compares an analog input voltage Vin with the reference voltage Vref to convert the analog input voltage Vin to a digital output value Dout. A measured value storing circuit stores a measured value of the reference voltage Vref in advance and outputs the stored measured value. A user of an A/D converter corrects the digital output value Dout from the A/D converting circuit by use of the measured value of the reference voltage Vref outputted from the measured value storing circuit, thereby obtaining a digital value representing the analog input voltage Vin accurately irrespective of the accuracy of the reference voltage Vref.Type: ApplicationFiled: March 24, 2006Publication date: August 10, 2006Inventors: Kazuyoshi Arimura, Atsushi Hayakawa, Hidekiyo Ozawa
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Patent number: 7075463Abstract: A reference voltage generating circuit generates a reference voltage Vref. An A/D converting circuit compares an analog input voltage Vin with the reference voltage Vref to convert the analog input voltage Vin to a digital output value Dout. A measured value storing circuit stores a measured value of the reference voltage Vref in advance and outputs the stored measured value. A user of an A/D converter corrects the digital output value Dout from the A/D converting circuit by use of the measured value of the reference voltage Vref outputted from the measured value storing circuit, thereby obtaining a digital value representing the analog input voltage Vin accurately irrespective of the accuracy of the reference voltage Vref.Type: GrantFiled: September 24, 2004Date of Patent: July 11, 2006Assignee: Fujitsu LimitedInventors: Kazuyoshi Arimura, Atsushi Hayakawa, Hidekiyo Ozawa
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Patent number: 7012558Abstract: An amplifying circuit amplifies and outputs voltage difference between first external input voltage and voltage corresponding to second external input voltage. An A/D converting circuit converts the output voltage of the amplifying circuit into a digital value by comparing it with reference voltage, and outputs it. A bias circuit selects the second external input voltage or voltage obtained by adding bias voltage to the second external input voltage, according to the output voltage of the amplifying circuit, and outputs it as the voltage corresponding to second external input voltage. A first storing circuit prestores a measured value of the bias voltage, and outputs the stored value as a digital value whose bit number is greater than that of the digital value from the A/D converting circuit, when the voltage corresponding to second external input voltage is the voltage obtained by adding the bias voltage to the second external input voltage.Type: GrantFiled: December 29, 2004Date of Patent: March 14, 2006Assignee: Fujitsu LimitedInventors: Kazuyoshi Arimura, Atsushi Hayakawa, Hidekiyo Ogawa
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Publication number: 20050258995Abstract: A reference voltage generating circuit generates a reference voltage Vref. An A/D converting circuit compares an analog input voltage Vin with the reference voltage Vref to convert the analog input voltage Vin to a digital output value Dout. A measured value storing circuit stores a measured value of the reference voltage Vref in advance and outputs the stored measured value. A user of an A/D converter corrects the digital output value Dout from the A/D converting circuit by use of the measured value of the reference voltage Vref outputted from the measured value storing circuit, thereby obtaining a digital value representing the analog input voltage Vin accurately irrespective of the accuracy of the reference voltage Vref.Type: ApplicationFiled: September 24, 2004Publication date: November 24, 2005Inventors: Kazuyoshi Arimura, Atsushi Hayakawa, Hidekiyo Ozawa
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Patent number: 6903591Abstract: A phase shift circuit that generates a phase shift signal whose amplitude matches at a plurality of frequencies without increasing the circuit area. The phase shifter circuit includes first and second differential amplifiers which generate first and second first phase shift signals having a first amplitude at a first frequency. A third differential amplifier is connected in parallel to the first differential amplifier. The third differential amplifier generates a third phase shift signal having substantially the same amplitude as the first amplitude at a second frequency. The first differential amplifier is activated in accordance with the first frequency and the third differential amplifier is activated in accordance with the second frequency.Type: GrantFiled: July 24, 2002Date of Patent: June 7, 2005Assignee: Fujitsu LimitedInventors: Kazuyoshi Arimura, Tsuyoshi Moribe
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Patent number: 6727771Abstract: A semiconductor integrated circuit device includes an orthogonal modulator that maintains carrier leak characteristics regardless of attenuation of an output signal level. The orthogonal modulator includes a phase shifter circuit and generates a modulation signal. An auto gain controller amplifies the modulation signal to generate an amplified modulation signal. A gain adjusting circuit adjusts a gain of the phase shifter circuit in accordance with a control signal.Type: GrantFiled: October 9, 2001Date of Patent: April 27, 2004Assignee: Fujitsu LimitedInventors: Tsuyoshi Moribe, Kazuyoshi Arimura, Susumu Kato
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Publication number: 20030017812Abstract: It is intended to provide a frequency multiplier capable of switching as appropriate among frequency signals having frequencies obtained by multiplying prescribed multiplication numbers with low current consumption and a simple circuit configuration in effectively utilizing frequencies in radio communication equipment. The base terminals of an input differential pair are biased by respective voltage sources, and an input frequency signal is input to one of the base terminals. The differential output terminals are connected to the base terminals of next-stage buffer circuit transistors, and their emitter terminals are connected to respective diodes. A full-wave-rectified signal, which is obtained at the connecting point of the cathode terminals of the diodes, is input to a comparison differential pair, which produces an output frequency signal by comparing the full-wave-rectified signal with a reference voltage.Type: ApplicationFiled: February 5, 2002Publication date: January 23, 2003Applicant: FREQUENCY MULTIPLIERInventor: Kazuyoshi Arimura
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Publication number: 20020180504Abstract: A phase shift circuit that generates a phase shift signal whose amplitude matches at a plurality of frequencies without increasing the circuit area. The phase shifter circuit includes first and second differential amplifiers which generate first and second first phase shift signals having a first amplitude at a first frequency. A third differential amplifier is connected in parallel to the first differential amplifier. The third differential amplifier generates a third phase shift signal having substantially the same amplitude as the first amplitude at a second frequency. The first differential amplifier is activated in accordance with the first frequency and the third differential amplifier is activated in accordance with the second frequency.Type: ApplicationFiled: July 24, 2002Publication date: December 5, 2002Applicant: FUJITSU LIMITEDInventors: Kazuyoshi Arimura, Tsuyoshi Moribe
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Patent number: 6466064Abstract: It is intended to provide a compact circuit configuration used for a frequency multiplier device, suitable to selectively output among a plurality of multiplied frequencies, with less power consumption. The frequency multiplier device uses an input frequency signal f and an output multiplied signal nf to form original signals a and c, as well as phase shifted signals b and d that are phase shifted to ±&pgr;/2 from the original signals a and c, the signals are mixed in a mixer circuits 16 and 17 and summed in a summing amplifier 18 to generate an output frequency signal fOUT. The phase inverter circuit (differential amplifier circuit) 14 and selector circuit (SEL1) 33) controls the phase inversion of one of signals to selectively output one of mixed frequencies (n±1)f as the output frequency signal fOUT.Type: GrantFiled: August 28, 2001Date of Patent: October 15, 2002Assignee: Fujitsu LimitedInventors: Yasuhiro Kurogouchi, Kazuyoshi Arimura, Yoshinobu Hattori
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Patent number: 6452434Abstract: A phase shift circuit that generates a phase shift signal whose amplitude matches at a plurality of frequencies without increasing the circuit area. The phase shifter circuit includes first and second differential amplifiers which generate first and second first phase shift signals having a first amplitude at a first frequency. A third differential amplifier is connected in parallel to the first differential amplifier. The third differential amplifier generates a third phase shift signal having substantially the same amplitude as the first amplitude at a second frequency. The first differential amplifier is activated in accordance with the first frequency and the third differential amplifier is activated in accordance with the second frequency.Type: GrantFiled: September 25, 2000Date of Patent: September 17, 2002Assignee: Fujitsu LimitedInventors: Kazuyoshi Arimura, Tsuyoshi Moribe
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Publication number: 20020125924Abstract: It is intended to provide a compact circuit configuration used for a frequency multiplier device, suitable to selectively output among a plurality of multiplied frequencies, with less power consumption. The frequency multiplier device uses an input frequency signal f and an output multiplied signal nf to form original signals a and c, as well as phase shifted signals b and d that are phase shifted to ±&pgr;/2 from the original signals a and c, the signals are mixed in a mixer circuits 16 and 17 and summed in a summing amplifier 18 to generate an output frequency signal fOUT. The phase inverter circuit (differential amplifier circuit) 14 and selector circuit (SEL1) 33) controls the phase inversion of one of signals to selectively output one of mixed frequencies (n±1) f as the output frequency signal fOUT.Type: ApplicationFiled: August 28, 2001Publication date: September 12, 2002Applicant: FUJITSU LIMITEDInventors: Yasuhiro Kurogouchi, Kazuyoshi Arimura, Yoshinobu Hattori
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Publication number: 20020074560Abstract: A semiconductor integrated circuit device includes an orthogonal modulator that maintains carrier leak characteristics regardless of attenuation of an output signal level. The orthogonal modulator includes a phase shifter circuit and generates a modulation signal. An auto gain controller amplifies the modulation signal to generate an amplified modulation signal. A gain adjusting circuit adjusts a gain of the phase shifter circuit in accordance with a control signal.Type: ApplicationFiled: October 9, 2001Publication date: June 20, 2002Applicant: Fujitsu LimitedInventors: Tsuyoshi Moribe, Kazuyoshi Arimura, Susumu Kato
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Patent number: 5539302Abstract: A reference power supply includes an amplifier having an output terminal and a reference voltage source for providing the amplifier with a constant voltage. The amplifier amplifies the constant voltage to produce a load-driving reference voltage at the output terminal. The amplifier includes first and second constant current sources and a first transistor as an output transistor having an emitter connected to a high-potential power supply, a collector connected to the output terminal and a base connected to the second constant current source. A resistor circuit is provided between the collector of the first transistor and the low-potential power supply. The amplifier also includes first, second and third current mirror circuits. The first current mirror circuit has second and third transistors. The second transistor has an emitter connected to the resistor circuit and the third transistor has an emitter connected to the reference voltage source.Type: GrantFiled: October 14, 1994Date of Patent: July 23, 1996Assignees: Fujitsu Limited, Fujitsu VLSI LimitedInventors: Kyuichi Takimoto, Kazuyoshi Arimura