Patents by Inventor Kazuyoshi Kikuta
Kazuyoshi Kikuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7576585Abstract: A delay circuit, including: a plurality of first delay units coupled in series and each configured to generate a delay time that is approximately double a unit delay time; a second delay unit configured to generate the unit delay time and coupled to a last stage of the plurality of first delay units; and a selector configured to select either an output signal of the last stage of the plurality of first delay units or an output signal of the second delay unit, wherein an external input signal is input to the first delay unit and to each second delay unit, and the first delay unit and the second delay unit each include a switch circuit configured to output with a delay either an output signal of a previous stage delay unit or the external input signal.Type: GrantFiled: March 12, 2008Date of Patent: August 18, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Shigetaka Asano, Kazuyoshi Kikuta
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Publication number: 20080224751Abstract: A delay circuit, including: a plurality of first delay units coupled in series and each configured to generate a delay time that is approximately double a unit delay time; a second delay unit configured to generate the unit delay time and coupled to a last stage of the plurality of first delay units; and a selector configured to select either an output signal of the last stage of the plurality of first delay units or an output signal of the second delay unit, wherein an external input signal is input to the first delay unit and to each second delay unit, and the first delay unit and the second delay unit each include a switch circuit configured to output with a delay either an output signal of a previous stage delay unit or the external input signal.Type: ApplicationFiled: March 12, 2008Publication date: September 18, 2008Applicant: Fujitsu LimitedInventors: Shigetaka ASANO, Kazuyoshi Kikuta
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Patent number: 6671112Abstract: A digital arithmetic operation circuit includes a plurality of arithmetic operation blocks, a control signal generator and a selector. The plurality of arithmetic operation blocks receive a plurality of digital input signals and perform different arithmetic operations on the received digital input signals, in parallel, to output operation result signals. The a control signal generator receives a plurality of digital input signals and generates a control signal based on the digital input signals. The selector selects one of the operation result signals, in response to the control signal, to output the selected operation result signal. After the control signal generator supplies the control signal to the selector, the selector outputs the selected operation result signal as soon as the selected operation result signal is supplied to the selector.Type: GrantFiled: December 21, 2001Date of Patent: December 30, 2003Assignee: Fujitsu LimitedInventors: Hiroko Murakami, Masaru Sawada, Manabu Nakano, Kazuyoshi Kikuta
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Publication number: 20030088834Abstract: A digital arithmetic operation circuit includes a plurality of arithmetic operation blocks, a control signal generator and a selector. The plurality of arithmetic operation blocks receive a plurality of digital input signals and perform different arithmetic operations on the received digital input signals, in parallel, to output operation result signals. The a control signal generator receives a plurality of digital input signals and generates a control signal based on the digital input signals. The selector selects one of the operation result signals, in response to the control signal, to output the selected operation result signal. After the control signal generator supplies the control signal to the selector, the selector outputs the selected operation result signal as soon as the selected operation result signal is supplied to the selector.Type: ApplicationFiled: December 21, 2001Publication date: May 8, 2003Inventors: Hiroko Murakami, Masaru Sawada, Manabu Nakano, Kazuyoshi Kikuta
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Patent number: 6377416Abstract: A digital arithmetic operation circuit includes a plurality of arithmetic operation blocks, a control signal generator and a selector. The plurality of arithmetic operation blocks receive a plurality of digital input signals and perform different arithmetic operations on the received digital input signals, in parallel, to output operation result signals. The a control signal generator receives a plurality of digital input signals and generates a control signal based on the digital input signals. The selector selects one of the operation result signals, in response to the control signal, to output the selected operation result signal. After the control signal generator supplies the control signal to the selector, the selector outputs the selected operation result signal as soon as the selected operation result signal is supplied to the selector.Type: GrantFiled: November 17, 1998Date of Patent: April 23, 2002Assignee: Fujitsu LimitedInventor: Kazuyoshi Kikuta
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Patent number: 5604723Abstract: This invention relates to a method and apparatus for reading out a synchronizing signal recorded in a data portion of each of a number of sectors stored in a recording medium such as an optical disc, a write-in-once type magneto-optical disc and so on. Even when detection of a synchronizing a signal has failed, the succeeding re-synchronizing signal can be detected reliably so that, although a first one divided unit portion of data is dropped out, data following the re-synchronizing signal can be read out positively, thus reducing data read error rate.Type: GrantFiled: January 17, 1991Date of Patent: February 18, 1997Assignees: Fujitsu Limited, Fujitsu VLSI LimitedInventor: Kazuyoshi Kikuta
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Patent number: 4975593Abstract: A single-chip microcomputer has external terminals outputting a system clock signal, an address signal, and a data signals. External equipment such as an external memory is operated by address and signal which are output when the system clock signal changes. In the single-chip microcomputer of this invention, the operation of an address signal output circuit and that of a data signal output circuit are controlled by a signal output from a digital delay circuit which receives the system clock signal. According to this circuit construction, the hold time between the change in the system clock and the change in the address and data signals is determined by the delay circuit which exhibits a digital operation, so that the hold time can be set accurately without being affected adversely by any variation in the circuit elements due to the manufacturing process, or by temperature changes.Type: GrantFiled: October 11, 1988Date of Patent: December 4, 1990Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering, Ltd.Inventors: Keiichi Kurakazu, Haruo Keida, Kazuyoshi Kikuta