Abstract: Provided is a supply-and-demand management apparatus including: a result management unit that manages a power supply result indicating a result of power supplied among a plurality of customers of a community; and a deriving unit that derives, based on power supply results from a first customer to other customers from among the plurality of customers, an incentive to supply power from the first customer to a second customer from among the other customers.

Abstract: A battery includes: a power generation element including battery cells which are electrically connected in parallel and stacked, and each of which includes an electrode layer, a counter-electrode layer, and a solid electrolyte layer located between the electrode layer and the counter-electrode layer; an electrode insulating layer covering an electrode layer among the electrode layers at a side surface of the power generation element; and a counter-electrode terminal covering the side surface and the electrode insulating layer, and electrically connected to a counter-electrode layer among the counter-electrode layers.

Abstract: A battery includes: a power generation element including battery cells each of which includes an electrode layer, a counter-electrode layer, and a solid electrolyte layer located between the electrode layer and the counter-electrode layer, and which are electrically connected in parallel and stacked; an insulating member covering an electrode layer at a side surface of the power generation element; and a terminal electrode covering the side surface and the insulating member, and electrically connected to a counter-electrode layer, in which the power generation element includes: a first parallel unit that includes first battery cells and has both ends in a stacking direction at each of which a counter-electrode layer is located; and a second parallel unit that includes second battery cells, has both ends in the stacking direction at each of which an electrode layers is located, and is stacked on the first parallel unit.

Abstract: A motor-related information processing circuit includes acquisition circuitry, first writing circuitry, and second writing circuitry. The acquisition circuitry acquires motor-related information regarding an operational state of a motor when the motor is driven. The first writing circuitry writes the motor-related information to a volatile memory after the motor-related information is acquired. The second writing circuitry writes the motor-related information stored in the volatile memory to a non-volatile memory when driving of the motor is stopped.

Abstract: Provided is an abnormality prediction system and an abnormality prediction method that are capable of predicting an abnormality occurring in a die that is used in a press machine.

Abstract: Provided is an abnormality prediction system and an abnormality prediction method that are capable of predicting an abnormality occurring in a die that is used in a press machine.

Abstract: A data processing system including: a memory controller; and a memory connected to said memory controller; wherein said memory controller includes a rendering circuit thereby to execute a rendering command generating display data based on graphic data provided after processing a program in a CPU, and stores said display data in said memory.

Abstract: A data processing system including: a memory controller; and a memory connected to said memory controller; wherein said memory controller includes a rendering circuit thereby to execute a rendering command generating display data based on graphic data provided after processing a program in a CPU, and stores said display data in said memory.

Abstract: A graphic processing apparatus for generating, display or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column address within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.

Abstract: A graphics processor comprises: a light source table holding light source data; a conversion unit for converting the light source data to be set in the light source table from a float type (single-precision floating point real number type) into an int type (integer type); an inner product calculation unit for calculating the inner products of normal directions, light source directions and sight line directions at the vertices based on the light source data; and a color calculation unit for performing light source computations based on the calculated inner products to determine the colors of the vertices.

Abstract: A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.

Abstract: A graphic processing apparatus for generating, display or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column address within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.

Abstract: In order to assure that a plurality of circuits such as a CPU I/F circuit, a rendering circuit, a video input circuit and a display circuit, which are each required to always complete a processing within a prescribed time, are each assured the ability to make as many accesses to a memory as required to complete the processing within the prescribed time, it is necessary to arbitrate a contention for an access to the memory through an internal bus among the circuits by employing a bus control circuit wherein priority levels assigned to the circuits to make an access to the internal bus are dynamically changed by comparing degrees of access urgency among the circuits. In this way, circuits that each have to always complete theirs processing within a prescribed time are assured the ability to make as many accesses to the memory as required to complete the processing within the prescribed time even if a plurality of such circuits do exist.

Abstract: A graphics processor comprises: a light source table holding light source data; a conversion unit for converting the light source data to be set in the light source table from a float type (single-precision floating point real number type) into an int type (integer type); an inner product calculation unit for calculating the inner products of normal directions, light source directions and sight line directions at the vertices based on the light source data; and a color calculation unit for performing light source computations based on the calculated inner products to determine the colors of the vertices.

Abstract: A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.

Abstract: A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.

Abstract: An information providing system is capable of rendering map-information services even if the size of a free area in a memory employed in a terminal becomes small, disallowing all details of a map to be downloaded. A server employed in the information providing system has a search engine for searching a map data base for a map suitable for a destination and the present position of the terminal as received from the terminal, a route computing unit for computing a guide route from the present position to the destination, a map display location determination unit for determining a location at which route information including a map based on the calculated guide route is to be transmitted to the terminal and a thinning determination unit for thinning the information to be transmitted based on information on the terminal received from the terminal. The thinning determination unit has a priority-level definition table for defining priority levels assigned to map elements stored in the map data base.

Abstract: A rendering processor having a plurality of DDA control circuits such that in each DDA circuit, the coordinates of source and destination images and gradation values are computed. Depending on the computation result, source and destination data to the raster arithmetic unit are generated so as to control the raster arithmetic unit, which enables a plurality of pixels to be generated and to be written in the memory during a memory access.

Abstract: A graphics system which accelerates generation of pixels including transparent objects by simply adding more rendering devices. The system has composition means and a plurality of rendering devices each comprising a geometric processor, a rendering processor and a frame memory that holds color, depth and weight data in a screen bit map format. Given a plurality of sets of color, depth and weight data about any one pixel position from the frame memories, the composition means first compares the depth data, and multiplies successively the weight and color data starting with those corresponding to the depth data closest to the foreground, thereby generating new pixel data. The system thus permits merging of transparent objects.

Abstract: A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.