Patents by Inventor Kazuyoshi Koga

Kazuyoshi Koga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10910838
    Abstract: An energy management device comprises a first supply/demand information acquisition unit, a second supply/demand information acquisition unit, and a supply/demand management unit configured to determine, based on the first supply/demand information and the second supply/demand information, at least one of (i) an upper limit value of a power amount that the hydrogen generation system can receive from a power grid during a certain period, (ii) a target value of an amount of hydrogen that the hydrogen generation system generates during the certain period, (iii) an upper limit value of a power amount that each of the one or plurality of tri-generation systems can transmit to the power grid during the certain period, and (iv) a target value of a power amount that each of the one or plurality of tri-generation systems generates during the certain period.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 2, 2021
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Yutaka Tsuji, Yuji Yamamoto, Jun Ishikawa, Kazuyoshi Miyajima, Takayuki Yamada, Yuiko Koga, Shigeaki Esaka
  • Publication number: 20210021132
    Abstract: An energy management device comprises a first supply/demand information acquisition unit, a second supply/demand information acquisition unit, and a supply/demand management unit configured to determine, based on the first supply/demand information and the second supply/demand information, at least one of (i) an upper limit value of a power amount that the hydrogen generation system can receive from a power grid during a certain period, (ii) a target value of an amount of hydrogen that the hydrogen generation system generates during the certain period, (iii) an upper limit value of a power amount that each of the one or plurality of tri-generation systems can transmit to the power grid during the certain period, and (iv) a target value of a power amount that each of the one or plurality of tri-generation systems generates during the certain period.
    Type: Application
    Filed: March 30, 2018
    Publication date: January 21, 2021
    Inventors: Yutaka TSUJI, Yuji YAMAMOTO, Jun ISHIKAWA, Kazuyoshi MIYAJIMA, Takayuki YAMADA, Yuiko KOGA, Shigeaki ESAKA
  • Publication number: 20210006071
    Abstract: Provided is a supply-and-demand management apparatus including: a result management unit that manages a power supply result indicating a result of power supplied among a plurality of customers of a community; and a deriving unit that derives, based on power supply results from a first customer to other customers from among the plurality of customers, an incentive to supply power from the first customer to a second customer from among the other customers.
    Type: Application
    Filed: September 3, 2020
    Publication date: January 7, 2021
    Inventors: Takayuki YAMADA, Koichiro TAKEMASA, Kazuyoshi MIYAJIMA, Keiichi TAKIKAWA, Yuiko KOGA
  • Publication number: 20200403444
    Abstract: Included are: a performance information obtaining unit that obtains, for each of a plurality of first power customers that configure a first community, information about a power interchange performance between the first power customer and the first community; a contribution degree determination unit that determines a contribution degree of at least one of the plurality of first power customers to a surplus power amount of the first community in a certain time period, based on information about the performance obtained by the performance information obtaining unit.
    Type: Application
    Filed: September 8, 2020
    Publication date: December 24, 2020
    Inventors: Takayuki YAMADA, Koichiro TAKEMASA, Kazuyoshi MIYAJIMA, Keiichi TAKIKAWA, Yuiko KOGA
  • Publication number: 20200112278
    Abstract: A motor-related information processing circuit includes acquisition circuitry, first writing circuitry, and second writing circuitry. The acquisition circuitry acquires motor-related information regarding an operational state of a motor when the motor is driven. The first writing circuitry writes the motor-related information to a volatile memory after the motor-related information is acquired. The second writing circuitry writes the motor-related information stored in the volatile memory to a non-volatile memory when driving of the motor is stopped.
    Type: Application
    Filed: February 7, 2018
    Publication date: April 9, 2020
    Applicant: Nidec Corporation
    Inventor: Kazuyoshi KOGA
  • Patent number: 10478887
    Abstract: Provided is an abnormality prediction system and an abnormality prediction method that are capable of predicting an abnormality occurring in a die that is used in a press machine.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: November 19, 2019
    Assignees: NIDEC-SHIMPO CORPORATION, NIDEC CORPORATION
    Inventors: Tetsuya Iwakuro, Takayuki Sawada, Masayuki Otani, Kazuyoshi Koga, Takafumi Maeda, Takeshi Honda, Nobuyuki Kita
  • Publication number: 20170036261
    Abstract: Provided is an abnormality prediction system and an abnormality prediction method that are capable of predicting an abnormality occurring in a die that is used in a press machine.
    Type: Application
    Filed: July 7, 2016
    Publication date: February 9, 2017
    Inventors: Tetsuya IWAKURO, Takayuki SAWADA, Masayuki OTANI, Kazuyoshi KOGA, Takafumi MAEDA, Takeshi HONDA, Nobuyuki KITA
  • Patent number: 7602389
    Abstract: A data processing system including: a memory controller; and a memory connected to said memory controller; wherein said memory controller includes a rendering circuit thereby to execute a rendering command generating display data based on graphic data provided after processing a program in a CPU, and stores said display data in said memory.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: October 13, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Koyo Katsura, Yasushi Fukunaga, Ryo Fujita, Kazuyoshi Koga, Takehiko Nishida
  • Publication number: 20060203000
    Abstract: A data processing system including: a memory controller; and a memory connected to said memory controller; wherein said memory controller includes a rendering circuit thereby to execute a rendering command generating display data based on graphic data provided after processing a program in a CPU, and stores said display data in said memory.
    Type: Application
    Filed: March 2, 2006
    Publication date: September 14, 2006
    Inventors: Koyo Katsura, Yasushi Fukunaga, Ryo Fujita, Kazuyoshi Koga, Takehiko Nishida
  • Patent number: 7019751
    Abstract: A graphic processing apparatus for generating, display or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column address within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: March 28, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Koyo Katsura, Yasushi Fukunaga, Ryo Fujita, Kazuyoshi Koga, Takehiko Nishida
  • Patent number: 6756981
    Abstract: A graphics processor comprises: a light source table holding light source data; a conversion unit for converting the light source data to be set in the light source table from a float type (single-precision floating point real number type) into an int type (integer type); an inner product calculation unit for calculating the inner products of normal directions, light source directions and sight line directions at the vertices based on the light source data; and a color calculation unit for performing light source computations based on the calculated inner products to determine the colors of the vertices.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: June 29, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Katsunori Suzuki, Ryo Fujita, Kazuyoshi Koga, Yuichi Abe, Mitsuru Soga, Kazuhisa Takami, Koyo Katsura, Hideki Fujii, Kazunori Oniki
  • Patent number: 6704019
    Abstract: A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
    Type: Grant
    Filed: April 17, 2002
    Date of Patent: March 9, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Koyo Katsura, Yasushi Fukunaga, Ryo Fujita, Kazuyoshi Koga, Takehiko Nishida
  • Publication number: 20040027354
    Abstract: A graphic processing apparatus for generating, display or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column address within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
    Type: Application
    Filed: August 8, 2003
    Publication date: February 12, 2004
    Inventors: Koyo Katsura, Yasushi Fukunaga, Ryo Fujita, Kazuyoshi Koga, Takehiko Nishida
  • Patent number: 6600492
    Abstract: In order to assure that a plurality of circuits such as a CPU I/F circuit, a rendering circuit, a video input circuit and a display circuit, which are each required to always complete a processing within a prescribed time, are each assured the ability to make as many accesses to a memory as required to complete the processing within the prescribed time, it is necessary to arbitrate a contention for an access to the memory through an internal bus among the circuits by employing a bus control circuit wherein priority levels assigned to the circuits to make an access to the internal bus are dynamically changed by comparing degrees of access urgency among the circuits. In this way, circuits that each have to always complete theirs processing within a prescribed time are assured the ability to make as many accesses to the memory as required to complete the processing within the prescribed time even if a plurality of such circuits do exist.
    Type: Grant
    Filed: April 15, 1999
    Date of Patent: July 29, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuya Shimomura, Shigeru Matsuo, Kazuyoshi Koga, Koyo Katsura, Yasuhiro Nakatsuka, Kazushige Yamagishi
  • Publication number: 20020196254
    Abstract: A graphics processor comprises: a light source table holding light source data; a conversion unit for converting the light source data to be set in the light source table from a float type (single-precision floating point real number type) into an int type (integer type); an inner product calculation unit for calculating the inner products of normal directions, light source directions and sight line directions at the vertices based on the light source data; and a color calculation unit for performing light source computations based on the calculated inner products to determine the colors of the vertices.
    Type: Application
    Filed: August 20, 2002
    Publication date: December 26, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Katsunori Suzuki, Ryo Fujita, Kazuyoshi Koga, Yuichi Abe, Mitsuru Soga, Kazuhisa Takami, Koyo Katsura, Hideki Fujii, Kazunori Oniki
  • Publication number: 20020126125
    Abstract: A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
    Type: Application
    Filed: April 17, 2002
    Publication date: September 12, 2002
    Inventors: Koyo Katsura, Yasushi Fukunaga, Ryo Fujita, Kazuyoshi Koga, Takehiko Nishida
  • Patent number: 6377267
    Abstract: A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: April 23, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Koyo Katsura, Yasushi Fukunaga, Ryo Fujita, Kazuyoshi Koga, Takehiko Nishida
  • Patent number: 6324467
    Abstract: An information providing system is capable of rendering map-information services even if the size of a free area in a memory employed in a terminal becomes small, disallowing all details of a map to be downloaded. A server employed in the information providing system has a search engine for searching a map data base for a map suitable for a destination and the present position of the terminal as received from the terminal, a route computing unit for computing a guide route from the present position to the destination, a map display location determination unit for determining a location at which route information including a map based on the calculated guide route is to be transmitted to the terminal and a thinning determination unit for thinning the information to be transmitted based on information on the terminal received from the terminal. The thinning determination unit has a priority-level definition table for defining priority levels assigned to map elements stored in the map data base.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: November 27, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Kimiyoshi Machii, Kazuyoshi Koga, Shigeru Matsuo, Yoshitaka Atarashi, Soshiro Kuzunuki, Keiko Abe, Toshimi Yokota
  • Patent number: 6292196
    Abstract: A rendering processor having a plurality of DDA control circuits such that in each DDA circuit, the coordinates of source and destination images and gradation values are computed. Depending on the computation result, source and destination data to the raster arithmetic unit are generated so as to control the raster arithmetic unit, which enables a plurality of pixels to be generated and to be written in the memory during a memory access.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: September 18, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Yasushi Fukunaga, Ryo Fujita, Kazuyoshi Koga, Isao Yasuda, Takeshi Kato
  • Patent number: 6266072
    Abstract: A graphics system which accelerates generation of pixels including transparent objects by simply adding more rendering devices. The system has composition means and a plurality of rendering devices each comprising a geometric processor, a rendering processor and a frame memory that holds color, depth and weight data in a screen bit map format. Given a plurality of sets of color, depth and weight data about any one pixel position from the frame memories, the composition means first compares the depth data, and multiplies successively the weight and color data starting with those corresponding to the depth data closest to the foreground, thereby generating new pixel data. The system thus permits merging of transparent objects.
    Type: Grant
    Filed: October 3, 1997
    Date of Patent: July 24, 2001
    Assignee: Hitachi, LTD
    Inventors: Kazuyoshi Koga, Ryo Fujita, Koyo Katsura, Katsunori Suzuki, Toshiyuki Kuwana