Abstract: According to one embodiment, an information processing apparatus including a suspension/resume function includes a bus controller which controls a bus capable of transmitting data at a first transmission speed or a second transmission speed lower than the first transmission speed, a storage module which stores setting information for limiting a data transmission speed of the bus to the second transmission speed, an initializing module which initializes the bus controller so as to limit the data transmission speed of the bus to the second transmission speed if the setting information is stored in the storage module when the apparatus is activated or returned from a suspended state, and a controller which stores the setting information into the storage module and makes the apparatus transit to the suspended state and return from the suspended state, when the transmission speed of the bus is limited to the second transmission speed.

Abstract: According to one embodiment, an information processing apparatus includes a processor including a register file which holds physical registers to which general purpose registers provided by an instruction set architecture are assigned, a virtual register assigning unit which assigns a virtual address in the main memory space to a physical register in the register file based on a request from a program, and records a correspondence between each of the virtual addresses and a corresponding one of the physical registers in a virtual register conversion table, and an access converting unit which determines whether or not a virtual address to be accessed is recorded in the virtual register conversion table managed by the virtual register assigning unit, and executes, when the virtual address is recorded therein, processing of accessing the physical register of which a correspondence to the virtual address is recorded in the virtual register conversion table.

Abstract: According to one embodiment, an information processing apparatus including a suspension/resume function includes a bus controller which controls a bus capable of transmitting data at a first transmission speed or a second transmission speed lower than the first transmission speed, a storage module which stores setting information for limiting a data transmission speed of the bus to the second transmission speed, an initializing module which initializes the bus controller so as to limit the data transmission speed of the bus to the second transmission speed if the setting information is stored in the storage module when the apparatus is activated or returned from a suspended state, and a controller which stores the setting information into the storage module and makes the apparatus transit to the suspended state and return from the suspended state, when the transmission speed of the bus is limited to the second transmission speed.

Abstract: According to one embodiment, an information processing apparatus comprises a plurality of temperature transmission sections provided in each of first and second semiconductor circuits, and configure to transmit first measured temperature of one of the first and second semiconductor circuits to the other of first and second semiconductor circuits when the first measured temperature is higher than a threshold temperature, and a plurality of operation speed varying sections provided in each of the first and second semiconductor circuits configure to reduce operation speed of the processor circuit possessed by the other of first and second semiconductor circuits, when the received first measured temperature is higher than the second measured temperature of the other of the first and second semiconductor circuits.

Abstract: According to one embodiment, an information processing apparatus includes a first processor which has a first instruction set, a second processor which has a second instruction set, a storage unit which stores a program including a first program module which is described by using the second instruction set and causes the second processor to execute a first process including the arithmetic process, and a second program module which is described by using the first instruction set and causes the first processor to execute a process which is the same as the first process, and a control unit which switches a mode for executing the program between a first mode in which the first program module is assigned to the second processor and a second mode in which the second program module is assigned to the first processor.

Abstract: According to one embodiment, an information processing apparatus includes a processor including a register file which holds physical registers to which general purpose registers provided by an instruction set architecture are assigned, a virtual register assigning unit which assigns a virtual address in the main memory space to a physical register in the register file based on a request from a program, and records a correspondence between each of the virtual addresses and a corresponding one of the physical registers in a virtual register conversion table, and an access converting unit which determines whether or not a virtual address to be accessed is recorded in the virtual register conversion table managed by the virtual register assigning unit, and executes, when the virtual address is recorded therein, processing of accessing the physical register of which a correspondence to the virtual address is recorded in the virtual register conversion table.

Abstract: According to one embodiment, a power supply circuit normally generates a plurality of power supply voltages, which are to be used in an information processing apparatus, from a direct-current power supply voltage generated from an alternating-current power supply by an alternating-current adapter and generates the power supply voltages from a battery power supply when the alternating-current power supply is shut off. The power supply voltages include a specific power supply voltage to be used in a network controller. A power supply controller controls the power supply circuit to inhibit the specific power supply voltage from being applied to the network controller if the alternating-current power supply is shut off while a system operating state of the information processing apparatus is one of a sleep state and a shutdown state.

Abstract: A wireless communication apparatus conducts wireless communication of a spread spectrum communication system that performs frequency hopping using a plurality of frequency channels having different frequencies and defined in a usable frequency band. The apparatus includes a unit which detects a carrier of another wireless communication system that is predetermined, and a unit which excludes a frequency channel of the plurality of frequency channels in which the carrier of the wireless communication system is detected, from frequency channels targeted for the frequency hopping.

Abstract: A wireless communication apparatus performs wireless communication using a plurality of frequency channels. In order to prevent a radio signal from interfering with another wireless communication system, the apparatus includes a unit which detects an error rate of each of the plurality of frequency channels, a unit which determines whether the detected error rate is higher than a specific threshold value, and a unit which suspends use of a frequency channel whose error rate is determined to be higher than the threshold value.

Abstract: An information processing apparatus includes a unit for disabling an output of sound information, a unit for detecting a state of the sound information, and a unit for notifying a user of the state of the sound information detected with the unit for detecting the state by using information other than a sound.

Abstract: A wireless communication apparatus conducts wireless communication of a spread spectrum communication system that performs frequency hopping using a plurality of frequency channels having different frequencies and defined in a usable frequency band. The apparatus includes a unit which detects a carrier of another wireless communication system that is predetermined, and a unit which excludes a frequency channel of the plurality of frequency channels in which the carrier of the wireless communication system is detected, from frequency channels targeted for the frequency hopping.

Abstract: A wireless communication apparatus performs wireless communication using a plurality of frequency channels. In order to prevent a radio signal from interfering with another wireless communication system, the apparatus includes a unit which detects an error rate of each of the plurality of frequency channels, a unit which determines whether the detected error rate is higher than a specific threshold value, and a unit which suspends use of a frequency channel whose error rate is determined to be higher than the threshold value.

Abstract: A driving force distributing device is provided for distributing a driving force of an engine to the left and right wheels of a vehicle by bringing a pair of hydraulic clutches into and out of their engaged states. The distributing device includes a hydraulic pump mounted within a casing thereof and driven through gears by a half shaft connected to one of the wheels. An oil passage interconnects the hydraulic pump and the hydraulic clutches, the oil passage being defined in a casing. A valve block is coupled to an upper surface of the casing. Thus, the oil passages interconnecting the hydraulic pump and the hydraulic clutches of the driving force distributing device can be compactly formed.

Abstract: A sound codec has an encoded signal input/output terminal. This terminal is selectively connected to a modem codec. Due to this selective connection, a microphone and a speaker, both connected to a sound signal input/output terminal of the sound codec, are used as a transceiver of the speaker phone, and the sound codec is controlled to function as a speaker phone codec.

Abstract: A microcomputer includes a program memory storing a string of instructions for a program, a central processing unit executing each instruction read out from the program memory, an instruction memory having an address area different from the program memory, a serial communication unit responding to data supplied in series thereto and writing instructions into the instruction memory in synchronism with an operation of the central processing unit, and an interrupt control unit responding to an interrupt request to cause the central processing unit to suspend the execution of the program stored in the program memory and to then execute instructions read out from the instruction memory to output internal conditions.

Abstract: In a magnetic recording circuit with a bias current circuit adapted to superimpose a bias current from a bias oscillator on a recording signal and to supply a resultant signal to a magnetic head, there is provided a resistor for detecting the bias current flowing through the magnetic head, a rectifier circuit for rectifying and smoothing a signal developing across the resistor, and a control circuit for comparing the output voltage of the rectifier circuit with a reference voltage and producing an output signal which controls the oscillation level of the bias oscillator, whereby the bias current flowing through the magnetic head can automatically be set to a predetermined level. A variable resistor for adjustment of the bias current and adjustment step for the variable resistor can be dispensed with.

Abstract: A time constant circuit capable of switching the characteristic, which is realized by a combination of an equivalent resistor made up of a switched capacitor and an ordinary capacitor, comprises a capacitor of the switched capacitor or the time constant circuit connected in parallel to a series circuit including a switching device and an additional capacitor. The characteristic is switched by turning on and off the additional capacitor by the switching device. The direct connection of a plurality of equivalent resistors with a plurality of switched capacitors and ordinary capacitors makes up an equalizer. The capacitor making up a switched capacitor is connected with a switching device and an additional capacitor so that the frequency characteristic of the equalizer is switchable by turning on and off the switching device. Each of the capacitors making up the switched capacitors, the capacitors making up the time constant circuits and the additional capacitors has an end thereof grounded.

Abstract: A signal voltage dividing circuit in which two switched capacitors each including an input terminal, an output terminal and a capacitor connected selectively to the input terminal or the output terminal are connected in series and driven in opposite phase with each other. A holding capacitor is connected between the junction of the two switched capacitors and a reference potential. An input signal is supplied across the two switched capacitors to produce a divided output signal from the junction of the two switched capacitors.

Abstract: A video signal reproducing system comprising means for driving a web of recording medium such as a tape at a constant speed, a self-scanned linear photoelectronic image device disposed for scanning in a direction perpendicular to the traveling direction of the recording medium, a clock pulse generator for applying clock pulses to this image device, and a light source for illuminating the recording medium, whereby information optically recorded on the recording medium can be scanned in a two-dimensional fashion to reproduce a video signal such as a television signal.