Abstract: An operation-position detector having a tube that allows an ultrasonic signal to propagate therethrough. The tube has a plurality of holes capable of being selectively closed or opened by an operation and is provided with an ultrasonic transmitter-receiver arranged at a first end thereof. A signal processor drives the ultrasonic transmitter-receiver and causes an ultrasonic signal to propagate through the inside of the tube, receives a reflection signal corresponding to a closed or open state of each of the holes, and detects the state of each hole on the basis of the reflection signal, thereby detecting the operation position of an operation conducted by an operator.

Abstract: An operation-position detector having a tube that allows an ultrasonic signal to propagate therethrough. The tube has a plurality of holes capable of being selectively closed or opened by an operation and is provided with an ultrasonic transmitter-receiver arranged at a first end thereof. A signal processor drives the ultrasonic transmitter-receiver and causes an ultrasonic signal to propagate through the inside of the tube, receives a reflection signal corresponding to a closed or open state of each of the holes, and detects the state of each hole on the basis of the reflection signal, thereby detecting the operation position of an operation conducted by an operator.

Abstract: An operation-position detector having a tube that allows an ultrasonic signal to propagate therethrough. The tube has a plurality of holes capable of being selectively closed or opened by an operation and is provided with an ultrasonic transmitter-receiver arranged at a first end thereof. A signal processor drives the ultrasonic transmitter-receiver and causes an ultrasonic signal to propagate through the inside of the tube, receives a reflection signal corresponding to a closed or open state of each of the holes, and detects the state of each hole on the basis of the reflection signal, thereby detecting the operation position of an operation conducted by an operator.

Abstract: A wiring pattern circuit includes part of wiring between a module control circuit and a module. Since the wiring pattern circuit includes a PLD, the wiring thereof can be variably configured in accordance with the specifications of the module control circuit and the module. The construction of the module control circuit can be therefore facilitated. In addition, since a printed wiring pattern does not have to be provided separately for the test of each of a plurality of different modules, the test period, the labor and the cost involved during the test can be decreased.

Abstract: In a circuit board, when lands provided on a rear surface of a substrate are each separated into a mainland and a sub-land, warping or other defects of the substrate can be ignored when soldering, and the substrate can be mounted with a high bonding strength. On the rear surface of a module substrate, partitions are each provided to separate a metal film into the mainland and the sub-land. Accordingly, when the substrate is mounted on a motherboard, solder applied beforehand from each end-surface electrode to the mainland can be largely protruded downward from the mainland, and warping or other defects of the substrate can be ignored by this protruding portion of the solder. In addition, in the state in which the substrate is mounted, since the solder is pushed out from between the mainland and the motherboard and overflows the partition, both the mainland and the sub-land can be soldered to the motherboard side, and hence stable bonding can be obtained at a large bonding area.

Abstract: A wiring pattern circuit includes part of wiring between a module control circuit and a module. Since the wiring pattern circuit includes a PLD, the wiring thereof can be variably configured in accordance with the specifications of the module control circuit and the module. The construction of the module control circuit can be therefore facilitated. In addition, since a printed wiring pattern does not have to be provided separately for the test of each of a plurality of different modules, the test period, the labor and the cost involved during the test can be decreased.

Abstract: In a circuit board, when lands provided on a rear surface of a substrate are each separated into a mainland and a sub-land, warping or other defects of the substrate can be ignored when soldering, and the substrate can be mounted with a high bonding strength. On the rear surface of a module substrate, partitions are each provided to separate a metal film into the mainland and the sub-land. Accordingly, when the substrate is mounted on a motherboard, solder applied beforehand from each end-surface electrode to the mainland can be largely protruded downward from the mainland, and warping or other defects of the substrate can be ignored by this protruding portion of the solder. In addition, in the state in which the substrate is mounted, since the solder is pushed out from between the mainland and the motherboard and overflows the partition, both the mainland and the sub-land can be soldered to the motherboard side, and hence stable bonding can be obtained at a large bonding area.

Abstract: A blanking plate is attached to the bottom surfaces of a split board and a remaining board, which are separated from one bare board. After depositing solder paste on a back electrode of the split board, a solder ball is attached on the solder paste. The split board is then heated to melt the solder ball. The molten solder flows along the back electrode and an edge electrode into a through-hole. A portion of the molten solder swells out of the bottom surface of the bare board, and solidifies and bonds to the back electrode and the edge electrode.

Abstract: End-face through holes each comprising a concave-curved end-face opening groove and an end-face electrode covering the inner wall of the groove are formed in the end-faces of a substrate. Furthermore, a solder having a semi-circular shape is attached to the end-face electrode. The solder comprises an electrode facing portion facing the end-face electrode in the end-face groove, and a protuberant portion elongated from the electrode facing portion to protrude on the back-surface side of the substrate. Thereby, even if the substrate or the like is warped, a gap between the end-face electrode and the electrode pad of a mother board can be filled with the protuberant portion of the solder to connect the end-face electrode and the electrode pad to each other.

Abstract: A blanking plate is attached to the bottom surfaces of a split board and a remaining board, which are separated from one bare board. After depositing solder paste on a back electrode of the split board, a solder ball is attached on the solder paste. The split board is then heated to melt the solder ball. The molten solder flows along the back electrode and an edge electrode into a through-hole. A portion of the molten solder swells out of the bottom surface of the bare board, and solidifies and bonds to the back electrode and the edge electrode.

Abstract: A motherboard is provided with a through-hole in a region thereof on which a module is mounted in contact with the motherboard. Heat, generated when heating the motherboard and the module so as to connect with each other by soldering, can quickly dissipate, in a cooling process, through the through-hole from a substrate of the module in which the heat is likely to accumulate, whereby unevenness of temperature distribution through the module can be suppressed. By virtue of the through-hole provided in the region of the motherboard in which the heat is likely to accumulate, the heat can also quickly dissipate from the region of the motherboard, whereby the unevenness of temperature distribution through the motherboard can be alleviated. The module and the motherboard are prevented from warping due to the unevenness of temperature distribution, whereby unstable connection is avoided.

Abstract: A framing and voice decoder part outputs an error information. An error ratio monitoring part monitors a bit error ratio based on the error information. A sampling rate changing part decides a sampling rate based on the bit error ratio and changes a number of bits of each shift register in the differential detector part to adapt the sampling rate. A sampling clock selector part selects one clock signal among four different frequency clock signals based on the decision of the sampling rate changing part and gives selected clock signal to the differential detector part as a sampling clock. The differential detector part makes demodulation in DQPSK (Differential Quadrilateral Phase Shift Keying). Since the error ratio is always maintained within a predetermined extent, a good voice quality is obtained. Since the sampling rate will not increase to unnecessarily high levels, power saving can be achieved and a consumption of batteries is reduced.

Abstract: A framing and voice decoder part outputs an error information. An error ratio monitoring part monitors a bit error ratio based on the error information. A sampling rate changing part decides a sampling rate based on the bit error ratio and changes a number of bits of each shift register in the differential detector part to adapt the sampling rate. A sampling clock selector part selects one clock signal among four different frequency clock signals based on the decision of the sampling rate changing part and gives selected clock signal to the differential detector part as a sampling clock. The differential detector part makes demodulation in DQPSK (Differential Quadrilateral Phase Shift Keying). Since the error ratio is always maintained within a predetermined extent, a good voice quality is obtained. Since the sampling rate will not increase to unnecessarily high levels, power saving can be achieved and a consumption of batteries is reduced.

Abstract: A DQPSK delay detection circuit is provided that can securely reproduce stable clock signal. An absolute value circuit ABS(14) calculates an absolute value of I signal. An absolute value circuit ABS(15) calculates an absolute value of Q signal. Subtraction circuit(16) generates a P signal according to the difference between the absolute values of I signal and Q signal. Zero-cross detection circuit(11) detects zero-cross timing of the P signal to input it as a timing signal to the DPLL(64). The zero-cross timing of the P signal can be detected even when the data pattern of I or Q signal makes it impossible to detect the zero-cross timing from I and Q signal. Because the zero-cross timing of the P signal has a variation less than that of the zero-cross timing determined from I or Q signal, it is becomes possible to reproduce stable clock signals and in turn reliability of data demodulation can be improved.

Abstract: A DQPSK delay detection circuit includes a semi-synchronous detector synchronously detecting an input signal to obtain two demodulated signals, a low-pass filter for extracting a baseband signal from the demodulated signals, an A-D convertor sampling the baseband signal by a clock signal with a frequency 32 times higher than a symbol rate frequency and converting them to digital values with a predetermined number of quantization bits, a clock pulse generator generating clock signals synchronized with the baseband signal and having a frequency equal to and two times as high as the symbol rate frequency with a phase adjusted in accordance with a change of an eye pattern of an output of the A-D convertor, a data delay unit delaying the output of the A-D convertor by a time equivalent to one time slot according to a clock signal synchronized with the baseband signal and having a frequency equal to the symbol rate frequency, an operation unit generating signals I and Q from the output of the A-D convertor and a on