Patents by Inventor Kazuyoshi Satoh

Kazuyoshi Satoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10381931
    Abstract: In a control system of a boost converter and a control method of the control system, when a temperature of a current sensor of a boost converter is within a prescribed temperature range, an electronic control unit performs i) executing intermittent step-up control of the boost converter and learning of an offset value of the current sensor, and ii) controlling the boost converter using a corrected current value. The corrected current value is a value obtained by correcting a detected value of the current sensor using a correction value. The correction value is calculated using the learned offset value and the temperature of the current sensor.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: August 13, 2019
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Kazuyoshi Satoh, Yasuhiro Terao
  • Publication number: 20190181758
    Abstract: In a control system of a boost converter and a control method of the control system, when a temperature of a current sensor of a boost converter is within a prescribed temperature range, an electronic control unit performs i) executing intermittent step-up control of the boost converter and learning of an offset value of the current sensor, and ii) controlling the boost converter using a corrected current value. The corrected current value is a value obtained by correcting a detected value of the current sensor using a correction value.
    Type: Application
    Filed: August 21, 2018
    Publication date: June 13, 2019
    Applicant: Toyota Jidosha Kabushiki Kaisha
    Inventors: Kazuyoshi Satoh, Yasuhiro Terao
  • Patent number: 5298802
    Abstract: In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element.
    Type: Grant
    Filed: May 3, 1993
    Date of Patent: March 29, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Usami, Noboru Shiozawa, Toshio Yamada, Hiromasa Katoh, Kazuyoshi Satoh, Tohru Kobayashi, Tatsuya Kimura, Masato Hamamoto, Atsushi Shimizu, Kaoru Koyu
  • Patent number: 5283480
    Abstract: In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element.
    Type: Grant
    Filed: July 25, 1990
    Date of Patent: February 1, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Usami, Noboru Shiozawa, Toshio Yamada, Hiromasa Katoh, Kazuyoshi Satoh, Tohru Kobayashi, Tatsuya Kimura, Masato Hamamoto, Atsushi Shimizu, Kaoru Koyu
  • Patent number: 4999520
    Abstract: A semiconductor integrated circuit wherein an input circuit is formed by a phase split circuit consisting of a bipolar transistor which outputs an inverted output from the collector and non-inverted output from the emitter, the emitter follower output circuit is driven by an inverted output of the phase split circuit, meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit.
    Type: Grant
    Filed: March 30, 1989
    Date of Patent: March 12, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Usami, Noboru Shiozawa, Toshio Yamada, Hiromasa Katoh, Kazuyoshi Satoh, Tohru Kobayashi, Tatsuya Kimura, Masato Hamamoto, Atsushi Shimizu, Kaoru Koyu