Patents by Inventor Kazuyoshi Tomita
Kazuyoshi Tomita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240124712Abstract: A polycarbonate copolymer which has siloxane constituent units represented by any of formulae (1-1) to (1-4) and prescribed polycarbonate constituent units.Type: ApplicationFiled: November 21, 2023Publication date: April 18, 2024Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INC.Inventors: Kazuyoshi UERA, Kohei KAMATANI, Keisuke TOMITA, Hisato AKIMOTO
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Publication number: 20220267778Abstract: It was found that nucleic acids for the specific targeting sequences or nucleic acids having the specific sequences have superior suppression activities of MURF1 expression. Pharmaceutical compositions including the nucleic acids as active ingredient are useful for treating or preventing disease accompanied by one or more symptoms selected from the group consisting of decrease in muscle mass, decrease in muscle strength and muscle dysfunction.Type: ApplicationFiled: July 29, 2020Publication date: August 25, 2022Applicant: Shionogi & Co., Ltd.Inventors: Takahiro FUJIWARA, Kazuyoshi TOMITA, Kunitaka NASHIKI, Ayumi NAGASAWA, Ryo YOSHIMOTO, Takahito ITO
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Patent number: 10763333Abstract: A nitride semiconductor device may comprise a p-type layer. The nitride semiconductor device may comprise a first n-type voltage-blocking layer in contact with the p-type layer. The nitride semiconductor device may comprise a second n-type voltage-blocking layer in contact with the first n-type voltage-blocking layer and separated from the p-type layer by the first n-type voltage-blocking layer. A donor concentration in the first n-type voltage-blocking layer may be lower than a donor concentration in the second n-type voltage-blocking layer. A carbon concentration in the first n-type voltage-blocking layer may be lower than a carbon concentration in the second n-type voltage-blocking layer.Type: GrantFiled: February 26, 2019Date of Patent: September 1, 2020Assignee: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHOInventors: Kazuyoshi Tomita, Tetsuo Narita
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Publication number: 20190305090Abstract: A nitride semiconductor device may comprise a p-type layer. The nitride semiconductor device may comprise a first n-type voltage-blocking layer in contact with the p-type layer. The nitride semiconductor device may comprise a second n-type voltage-blocking layer in contact with the first n-type voltage-blocking layer and separated from the p-type layer by the first n-type voltage-blocking layer. A donor concentration in the first n-type voltage-blocking layer may be lower than a donor concentration in the second n-type voltage-blocking layer. A carbon concentration in the first n-type voltage-blocking layer may be lower than a carbon concentration in the second n-type voltage-blocking layer.Type: ApplicationFiled: February 26, 2019Publication date: October 3, 2019Applicant: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHOInventors: Kazuyoshi TOMITA, Tetsuo NARITA
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Patent number: 10381469Abstract: A semiconductor device includes a switching device having: a substrate configured by a semi-insulating material or a semiconductor; a channel forming layer on the substrate that is configured by a compound semiconductor mainly having a group III nitride; a gate structure configured by a gate electrode on the channel forming layer with a gate insulating film interposed therebetween; and a source electrode and a drain electrode on the channel forming layer at both sides of the gate structure respectively, a collapse inhibiting layer on the channel forming layer in an element region of the channel forming layer where the switching device is arranged that is configured by an insulating material; and a leakage inhibiting layer on the channel forming layer in an element isolation region of the channel forming layer surrounding the element region that is configured by an insulating material different from that of the collapse inhibiting layer.Type: GrantFiled: August 28, 2014Date of Patent: August 13, 2019Assignee: DENSO CORPORATIONInventors: Yoshinori Tsuchiya, Shinichi Hoshi, Kazuyoshi Tomita, Kenji Itoh, Masahito Kodama, Tsutomu Uesugi
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Patent number: 9818856Abstract: A semiconductor device includes a HEMT and a diode. The HEMT includes: a substrate having a GaN layer as a channel layer generating a two-dimensional electron gas and an AlGaN layer as a barrier layer on the GaN layer; a source electrode on the AlGaN layer ohmic contacting the AlGaN layer; a drain electrode on the AlGaN layer apart from the source electrode and ohmic contacting the AlGaN layer; an inter-layer insulating film on the AlGaN layer between the source electrode and the drain electrode; and a gate electrode on the inter-layer insulating film. The substrate includes an active layer region generating the two dimensional electron gas in the GaN layer. The diode includes an anode electrically connected to the gate electrode and a cathode electrically connected to the drain electrode.Type: GrantFiled: October 17, 2012Date of Patent: November 14, 2017Assignee: DENSO CORPORATIONInventors: Shinichi Hoshi, Shoji Mizuno, Tetsu Kachi, Tsutomu Uesugi, Kazuyoshi Tomita, Kenji Ito
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Patent number: 9728609Abstract: A step-flow growth of a group-III nitride single crystal on a silicon single crystal substrate is promoted. A layer of oxide oriented to a <111> axis of silicon single crystal is formed on a surface of a silicon single crystal substrate, and group-III nitride single crystal is crystallized on a surface of the layer of oxide. Thereupon, a <0001> axis of the group-III nitride single crystal undergoing crystal growth is oriented to a c-axis of the oxide. When the silicon single crystal substrate is provided with a miscut angle, step-flow growth of the group-III nitride single crystal occurs. By deoxidizing a silicon oxide layer formed at an interface of the silicon single crystal and the oxide, orientation of the oxide is improved.Type: GrantFiled: November 1, 2012Date of Patent: August 8, 2017Assignees: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, DENSO CORPORATIONInventors: Tetsuo Narita, Kenji Ito, Kazuyoshi Tomita, Nobuyuki Otake, Shinichi Hoshi, Masaki Matsui
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Patent number: 9536996Abstract: Teaching disclosed herein is an apparatus comprising a support layer. The support layer may be adapted for supporting a heat generator, wherein the support layer includes a flow passage. The flow passage may seal working fluid therein. The flow passage may extend along a thickness direction of the support layer.Type: GrantFiled: July 29, 2015Date of Patent: January 3, 2017Assignee: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHOInventors: Hirofumi Funabashi, Takashi Ozaki, Isao Aoyagi, Teruhisa Akashi, Yoshiteru Omura, Keiichi Shimaoka, Yutaka Nonomura, Norio Fujitsuka, Motohiro Fujiyoshi, Yoshiyuki Hata, Kanae Murata, Tetsuo Narita, Kazuyoshi Tomita
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Publication number: 20160372587Abstract: A semiconductor device includes a switching device having: a substrate configured by a semi-insulating material or a semiconductor; a channel forming layer on the substrate that is configured by a compound semiconductor mainly having a group III nitride; a gate structure configured by a gate electrode on the channel forming layer with a gate insulating film interposed therebetween; and a source electrode and a drain electrode on the channel forming layer at both sides of the gate structure respectively, a collapse inhibiting layer on the channel forming layer in an element region of the channel forming layer where the switching device is arranged that is configured by an insulating material; and a leakage inhibiting layer on the channel forming layer in an element isolation region of the channel forming layer surrounding the element region that is configured by an insulating material different from that of the collapse inhibiting layer.Type: ApplicationFiled: August 28, 2014Publication date: December 22, 2016Inventors: Yoshinori TSUCHIYA, Shinichi HOSHI, Kazuyoshi TOMITA, Kenji ITOH, Masahito KODAMA, Tsutomu UESUGI
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Publication number: 20160043066Abstract: Teaching disclosed herein is an apparatus comprising a support layer. The support layer may be adapted for supporting a heat generator, wherein the support layer includes a flow passage. The flow passage may seal working fluid therein. The flow passage may extend along a thickness direction of the support layer.Type: ApplicationFiled: July 29, 2015Publication date: February 11, 2016Inventors: Hirofumi FUNABASHI, Takashi OZAKI, Isao AOYAGI, Teruhisa AKASHI, Yoshiteru OMURA, Keiichi SHIMAOKA, Yutaka NONOMURA, Norio FUJITSUKA, Motohiro FUJIYOSHI, Yoshiyuki HATA, Kanae MURATA, Tetsuo NARITA, Kazuyoshi TOMITA
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Publication number: 20150053996Abstract: A step-flow growth of a group-III nitride single crystal on a silicon single crystal substrate is promoted. A layer of oxide oriented to a <111> axis of silicon single crystal is formed on a surface of a silicon single crystal substrate, and group-III nitride single crystal is crystallized on a surface of the layer of oxide. Thereupon, a <0001> axis of the group-III nitride single crystal undergoing crystal growth is oriented to a c-axis of the oxide. When the silicon single crystal substrate is provided with a miscut angle, step-flow growth of the group-III nitride single crystal occurs. By deoxidizing a silicon oxide layer formed at an interface of the silicon single crystal and the oxide, orientation of the oxide is improved.Type: ApplicationFiled: November 1, 2012Publication date: February 26, 2015Applicants: Kabushiki Kaisha Toyota Chuo Kenkyusho, Denso CorporationInventors: Tetsuo Narita, Kenji Ito, Kazuyoshi Tomita, Nobuyuki Otake, Shinichi Hoshi, Masaki Matsui
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Publication number: 20140231874Abstract: A semiconductor device includes a HEMT and a diode. The HEMT includes: a substrate having a GaN layer as a channel layer generating a two-dimensional electron gas and an AlGaN layer as a barrier layer on the GaN layer; a source electrode on the AlGaN layer ohmic contacting the AlGaN layer; a drain electrode on the AlGaN layer apart from the source electrode and ohmic contacting the AlGaN layer; an inter-layer insulating film on the AlGaN layer between the source electrode and the drain electrode; and a gate electrode on the inter-layer insulating film. The substrate includes an active layer region generating the two dimensional electron gas in the GaN layer. The diode includes an anode electrically connected to the gate electrode and a cathode electrically connected to the drain electrode.Type: ApplicationFiled: October 17, 2012Publication date: August 21, 2014Applicant: DENSO CORPORATIONInventors: Shinichi Hoshi, Shoji Mizuno, Tetsu Kachi, Tsutomu Uesugi, Kazuyoshi Tomita, Kenji Ito
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Patent number: 8420502Abstract: A method for producing a Group III-V semiconductor device, includes forming, on a base, a plurality of semiconductor devices isolated from one another, forming, through ion implantation, a high-resistance region in a surface layer of a side surface of each semiconductor device, after formation of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of the semiconductor device, bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer, and removing the base through the laser lift-off process.Type: GrantFiled: February 22, 2010Date of Patent: April 16, 2013Assignee: Toyoda Gosei Co., Ltd.Inventors: Masanobu Ando, Shigemi Horiuchi, Yoshinori Kinoshita, Kazuyoshi Tomita
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Publication number: 20100151612Abstract: A method for producing a Group III-V semiconductor device, includes forming, on a base, a plurality of semiconductor devices isolated from one another, forming, through ion implantation, a high-resistance region in a surface layer of a side surface of each semiconductor device, after formation of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of the semiconductor device, bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer, and removing the base through the laser lift-off process.Type: ApplicationFiled: February 22, 2010Publication date: June 17, 2010Applicant: TOYODA GOSEI CO., LTD.Inventors: Masanobu Ando, Shigemi Horiuchi, Yoshinori Kinoshita, Kazuyoshi Tomita
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Patent number: 7646036Abstract: An object of the invention is to prevent migration of silver contained in an electrode of a Group III nitride-based compound semiconductor light-emitting device. A positive electrode is formed on a p-type layer. In the positive electrode, an ITO light-transmitting electrode layer, a silver alloy reflecting electrode layer, a diffusion-preventing layer in which a Ti layer and a Pt layer are stacked, and a gold thick-film electrode are sequentially stacked on the p-type layer. The reflecting electrode layer made of a silver alloy contains palladium (Pd) and copper (Cu) as additives and also contains oxygen (O). By virtue of this structure, migration of silver from the silver alloy reflecting electrode layer and blackening of the interface between the silver alloy layer and the ITO light-transmitting electrode layer disposed thereunder are prevented, whereby light extraction efficiency can be enhanced.Type: GrantFiled: February 4, 2008Date of Patent: January 12, 2010Assignees: Kabushiki Kaisha Toyota Chuo Kenkyusho, Toyoda Gosei Co., Ltd.Inventors: Takahiro Kozawa, Kazuyoshi Tomita, Toshiya Uemura, Shigemi Horiuchi
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Publication number: 20080237629Abstract: A Group III-V semiconductor device bonded to a conductive support substrate, which device has a side surface whose surface layer has a high-resistance region formed through ion implantation.Type: ApplicationFiled: March 14, 2008Publication date: October 2, 2008Applicant: TOYODA GOSEI, CO., LTD.Inventors: Masanobu Ando, Shigemi Horiuchi, Yoshinori Kinoshita, Kazuyoshi Tomita
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Publication number: 20080185609Abstract: An object of the invention is to prevent migration of silver contained in an electrode of a Group III nitride-based compound semiconductor light-emitting device. An n-type AlxGayIn1-x-yN layer, a light-emitting layer, and a p-type AlxGayIn1-x-yN layer are formed on a dielectric substrate such as a sapphire substrate. After formation of these layers, the n-type AlxGayIn1-x-yN layer is exposed through etching or a similar technique, and an n-electrode is formed on the exposed area. A positive electrode is formed on the p-type layer. In the positive electrode, an ITO light-transmitting electrode layer, a silver alloy reflecting electrode layer, a diffusion-preventing layer in which a Ti layer and a Pt layer are stacked, and a gold thick-film electrode are sequentially stacked on the p-type layer. The reflecting electrode layer made of a silver alloy contains palladium (Pd) and copper (Cu) as additives and also contains oxygen (O).Type: ApplicationFiled: February 4, 2008Publication date: August 7, 2008Applicants: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYODA GOSEI CO., LTD.Inventors: Takahiro KOZAWA, Kazuyoshi TOMITA, Toshiya UEMURA, Shigemi HORIUCHI
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Patent number: 7342364Abstract: A light source comprising a light emitting diode comprising a GaN-based compound and having a single quantum well structure, and a driving voltage source for applying a pulse voltage to the light emitting diode, wherein a voltage at a low level of the pulse voltage is set to a voltage lower than a voltage at which a fall time of the light emitting diode is made the longest.Type: GrantFiled: September 15, 2005Date of Patent: March 11, 2008Assignee: Toyoda Gosei Co., Ltd.Inventors: Satoru Kato, Tetsu Kachi, Kazuyoshi Tomita, Hiroshi Ito, Masanori Kojima
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Patent number: 7163876Abstract: In the epitaxial growth process in which each growth region D is zoned by a mask 2 formed in grid pattern, because a consumption region C of the Group III nitride compound semiconductor is formed in the central portion of each band of the mask 2 between each adjacent edge portion of the growth region D, Group III or Group V raw material is never unnecessarily supplied to the edge portion of the growth region D. As a result, difference of Group III or Group V rare material supply amount to the edge portion and central portion of the device formation region D is suppressed and the edge portion of the device region may not be convexity.Type: GrantFiled: March 12, 2002Date of Patent: January 16, 2007Assignees: Toyoda Gosei Co., Ltd, Kabushiki Kaisha Toyota Chuo KenkyushoInventors: Seiji Nagai, Masayoshi Koike, Kazuyoshi Tomita
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Patent number: 7052979Abstract: When a substrate layer (desired semiconductor crystal) made of a group III nitride compound is grown on a base substrate comprising a lot of projection parts, a cavity in which a semiconductor crystal is not deposited may be formed between each projection part although it depends on conditions such as the size of each projection part, arranging interval between each projection part and crystal growth. So when the thickness of the substrate layer is sufficiently larger compared with the height of the projection part, inner stress or outer stress become easier to act intensively to the projection part. As a result, such stress especially functions as shearing stress toward the projection part. When the shearing stress becomes larger, the projection part is ruptured. So utilizing the shearing stress enables to separate the base substrate and the substrate layer easily.Type: GrantFiled: February 12, 2002Date of Patent: May 30, 2006Assignee: Toyoda Gosei Co., Ltd.Inventors: Seiji Nagai, Kazuyoshi Tomita, Shiro Yamazaki, Yuta Tezen, Toshio Hiramatsu