Abstract: In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to 1/100 or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

Abstract: There is provided a method for producing a spark plug in which welding strength between a noble metal tip and an electrode joined by laser welding can be restrained from becoming weak. A noble metal tip (90) to be joined to a center electrode (2) or ground electrode of a spark plug to form a spark discharge gap is resistance-welded to each electrode containing no noble metal and then laser-welded. In the noble metal tip (90) exposed under a severe environment involving spark discharge, a molten portion (80) formed in such a manner that a portion of the noble metal tip (90) and a portion of the electrode are melted by laser welding and a non-molten portion (95) on the noble metal tip (90) side are apt to be peeled from each other in a boundary surface (83) between the molten portion (80) and the non-molten portion (95).

Abstract: A ground-electrode spark portion 32 is formed from a noble metal which contains Pt as a main component, and is joined to a main metal portion of the ground electrode 4 via an alloy layer which has a thickness ranging from 0.5 ?m to 100 ?m and in which the noble metal that constitutes the ground-electrode spark portion 32 and the metal that constitutes the main metal portion of the ground electrode 4 are alloyed with each other. The ground-electrode spark portion 32 is configured such that a distal end surface 32t facing a spark discharge gap g is smaller in diameter than a bottom surface 32u joined to the ground electrode 4; and the distal end surface 32t is protrusively located beyond the side surface 4s of the ground electrode 4.

Abstract: In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to 1/100 or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

Abstract: An object of this invention is to prevent the NBTI degradation which may occur following the recent progress in miniaturization of the semiconductor device. By using a silicon nitride film, in which a concentration of Si—H bonds is not greater than 1×1021 cm?3, at least for a liner film or a second sidewall insulating film, the NBTI lifetime of the p-type MOS FET can be improved to be 1×109 seconds, which secures sufficient lifetime for the semiconductor integrated circuit device.

Abstract: A method for manufacturing a semiconductor device includes forming a first insulating film on a substrate, forming a second insulating film on the first insulating film, and forming a gate electrode on the second insulating film. Forming the second insulating film includes supplying film-forming materials and adsorbing the film-forming materials on the first insulating film, purging the film-forming materials that have not been adsorbed, supplying oxidants to oxidize the adsorbed film-forming materials, and purging the oxidants that have not contributed to oxidization. Forming the second insulating film is repeated in cycles, continuously, and the purging time of the oxidants in an initial number of the cycles is longer than the purging time of the oxidants in cycles following the initial number of cycles.

Abstract: A ground-electrode spark portion 32 is formed from a noble metal which contains Pt as a main component, and is joined to a main metal portion of the ground electrode 4 via an alloy layer which has a thickness ranging from 0.5 ?m to 100 ?m and in which the noble metal that constitutes the ground-electrode spark portion 32 and the metal that constitutes the main metal portion of the ground electrode 4 are alloyed with each other. The ground-electrode spark portion 32 is configured such that a distal end surface 32t facing a spark discharge gap g is smaller in diameter than a bottom surface 32u joined to the ground electrode 4; and the distal end surface 32t is protrusively located beyond the side surface 4s of the ground electrode 4.

Abstract: A gate insulating film on a silicon substrate of includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.

Abstract: In a miniaturized field effect transistor, the roughness of the interface between a gate dielectric film and a gate electrode is controlled on an atomic scale. The thickness variation of the gate dielectric film is lowered, whereby a field effect transistor with high mobility is manufactured. An increase in the mobility in the field effect transistor can be achieved not only in the case of using a conventional SiO2 thermal oxide film as the gate dielectric film but also in the case of using a high dielectric material for the gate dielectric film.

Abstract: A gate insulating film on a silicon substrate includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.

Abstract: An atomic layer deposition (ALD) apparatus capable of forming a conformal ultrathin-film layer with enhanced step coverage is disclosed. The apparatus includes an ALD reactor supporting therein a wafer, and a main pipe coupled thereto for constant supply of a carrier gas. This pipe has two parallel branch pipes. Raw material sources are connected by three-way valves to one branch pipe through separate pipes, respectively. Similarly, oxidant/reducer sources are coupled by three-way valves to the other branch pipe via independent pipes. ALD works by introducing one reactant gas at a time into the reactor while being combined with the carrier gas. The gas is “chemisorped” onto the wafer surface, creating a monolayer deposited. During the supply of a presently selected material gas from its source to a corresponding branch pipe, this gas passes through its own pipe independently of the others. An ALD method is also disclosed.

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: In a method for forming a semiconductor device, the major surface of a substrate is separated into a first element region for forming a first field-effect transistor and a second element region for forming a second field-effect transistor. A silicon nitride film is formed in each of the first and second element regions. Thereafter, the silicon nitride film formed in the second element region is removed, and the substrate is subjected to heat treatment in an ambient that contains nitrogen oxide. Thereby, the silicon nitride film in the first element region is oxidized to form an oxynitride film, and a silicon oxynitride film is formed in the second element region. Thereafter, a high-dielectric-constant film is formed on the silicon oxynitride films in each of the first and second element regions.

Abstract: A method of fabricating a semiconductor device, is provided including forming an insulating film having an opening portion on a substrate having a transistor, filling a conductive film in the opening portion, forming a reaction barrier film functioning to prevent a reaction on the insulating film, and forming a diffusion barrier film on the conductive film. Next a first electrode is formed on the diffusion barrier film, a ferroelectric film, including at least one element of the group consisting of lead, barium and bismuth is formed on the first electrode after the step of forming the reaction barrier film, and a second electrode is formed on the ferroelectric film.

Abstract: A semiconductor device of the present invention comprises: a silicon substrate; a gate insulating film on the silicon substrate; and a gate electrode on the gate insulating film, wherein the gate insulating film includes: a first insulating film; a second insulating film on the first insulating film; and a metal nitride film on the second insulating film. The metal nitride film may be either AlN or Hf3N4. The metal nitride film may include nitrides of two or more different metals.

Abstract: A gate insulating film on a silicon substrate includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.

Abstract: In a method for forming a semiconductor device, the major surface of a substrate is separated into a first element region for forming a first field-effect transistor and a second element region for forming a second field-effect transistor. A silicon nitride film is formed in each of the first and second element regions. Thereafter, the silicon nitride film formed in the second element region is removed, and the substrate is subjected to heat treatment in an ambient that contains nitrogen oxide. Thereby, the silicon nitride film in the first element region is oxidized to form an oxynitride film, and a silicon oxynitride film is formed in the second element region. Thereafter, a high-dielectric-constant film is formed on the silicon oxynitride films in each of the first and second element regions.

Abstract: In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to {fraction (1/100)} or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

Abstract: It is an object of the present invention to provide a fine memory cell structure preventing a reaction between an interlayer insulating film and a ferroelectric film and suitable for high integration. According to the invention, there is provided a structure in which a reaction barrier film 43 is interposed between a ferroelectric film 71 and an interlayer insulating film 32 and side walls of a diffusion barrier film 51 are not brought into direct contact with the ferroelectric film 71. Thereby, the reaction between the interlayer insulating film 32 and the ferroelectric film 71 can be restrained and exfoliation of the ferroelectric film 71 can be prevented.

Abstract: Disclosed are a semiconductor device which hardly experiences a reduction in mobility caused by scattering by the fixed charge existent in a gate insulating film while the EOT of a fine CMOS comprising the high-dielectric gate insulating film is reduced and which enables high integration, and a production process therefor. CMOS having no junction is formed on an SOI substrate and a high-dielectric gate insulating film is used as the gate insulating film of the CMOS. The feature of the CMOS device of the present invention is that the CMOS device is operated in an accumulation mode. Since a channel is formed several nm away from the surface of the substrate as compared with an ordinary device which operates in an inversion mode, a reduction in mobility caused by the fixed charge existent in the gate insulating film can be reduced.