Patents by Inventor Kazuyoshi Uemura

Kazuyoshi Uemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8484237
    Abstract: A terminal stores in a storage section content distributed from a server and a data access power for deleting a service that differ from a service to which the content belongs in association with each other. The terminal determines, when the stored content requests the deletion of the differing service that is indicated by the statement contained in the content, whether or not the content and the data access power are stored in the storage section in association with each other. When the terminal has determined that the content that requested the deletion of the differing service and the data access power are stored in the storage section in association with each other, the terminal deletes content that belongs to the differing service from the storage section.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: July 9, 2013
    Assignee: NEC Corporation
    Inventors: Kazuyoshi Uemura, Masanobu Nakamura
  • Publication number: 20110035362
    Abstract: A terminal stores in a storage section content distributed from a server and a data access power for deleting a service that differ from a service to which the content belongs in association with each other. The terminal determines, when the stored content requests the deletion of the differing service that is indicated by the statement contained in the content, whether or not the content and the data access power are stored in the storage section in association with each other. When the terminal has determined that the content that requested the deletion of the differing service and the data access power are stored in the storage section in association with each other, the terminal deletes content that belongs to the differing service from the storage section.
    Type: Application
    Filed: March 18, 2009
    Publication date: February 10, 2011
    Applicant: NEC CORPORATION
    Inventors: Kazuyoshi Uemura, Masanobu Nakamura
  • Patent number: 6337108
    Abstract: Disclosed is a powder paint composition that can form coating film having high corrosion resistance and excellent appearance even on a metal substrate surface containing non-flat portions and a process for forming multi-layer coats excellent both in corrosion resistance and top-coat adhesion using the powder paint composition. The powder paint composition comprises a) 30-55 parts by weight of a polyester resin having a hydroxyl value of 50-150, b) 1-20 parts by weight of a hydroxyl group-containing acrylic resin having a hydroxyl value of 30-150, c) 1-15 parts by weight of an epoxy resin, and d) 10-30 parts by weight of a urethodione ring-containing compound, based on 100 parts by weight of solid contents in the powder paint composition, the powder paint composition having an average particle size of 5-40 &mgr;m.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: January 8, 2002
    Assignees: Honda Giken Kogyo Kabushiki Kaisha, Nippon Paint Co., Ltd.
    Inventors: Masayuki Yamaguchi, Yukihide Yamashita, Norihiko Sudo, Shinji Seo, Kazuyoshi Uemura
  • Patent number: 6025035
    Abstract: This invention relates to a method for forming a coating film which comprises applying an epoxy resin powder coating (A) onto a substrate by electrostatic coating, half-baking the resultant uncured coat, applying a polyester resin powder coating (B) onto the half-baked coat by electrostatic coating, and baking the two uncured coats simultaneously, wherein the epoxy resin powder coating (A) and the polyester resin powder coating (B) is such that the gel time ratio [epoxy resin powder coating (A)]/[polyester resin powder coating (B)] at 180.degree. C. is 1/1 through 1/5, the gel time of the epoxy resin powder coating (A) at 180.degree. C. is 40 to 400 seconds, and the gel time of the polyester resin powder coating (B) at 180.degree. C. is not over 500 seconds.
    Type: Grant
    Filed: August 27, 1998
    Date of Patent: February 15, 2000
    Assignee: Nippon Paint Co., Ltd.
    Inventors: Shinji Seo, Hiroshi Oda, Kazuyoshi Uemura
  • Patent number: 5874883
    Abstract: A planar-type inductor that can restrain the maximum operable frequency from lowering even if the inductance part of the inductor is miniaturized. This inductor includes an insulating substructure and a patterned conductor layer having a predesigned geometric shape and formed on a chief surface of the substructure. The patterned conductor layer contains an inductance part for providing a wanted inductance value and a first lead part and a second lead part for electrically connecting the inductance part to an external circuit located outside the inductor. The inductance part has a first region and a second region located adjacent to each other at an interval. The inductor further includes a recess formed in the substructure between the first region and the second region of the inductance part. The recess extends along the first region and the second region. A parasitic capacitance between the first region and the second region is reduced due to the existence of the recess.
    Type: Grant
    Filed: July 18, 1996
    Date of Patent: February 23, 1999
    Assignee: NEC Corporation
    Inventors: Kazuyoshi Uemura, Kiyoshi Takahashi
  • Patent number: 5495125
    Abstract: It is an object of the present invention to provide a molded semiconductor device which allows its package to be mounted on an external circuit even if the width of the conductor of a high-frequency signal transmission line on a packaging substrate of an external circuit is large, when the molded semiconductor device is to be connected to the external circuit. A semiconductor chip 3 is mounted on a first metal member 2 by mounting solder of AuSn or the like by bonding. The semiconductor chip 3 has a high-frequency signal terminal connected to a second metal member 1 by a metal wire 4 of Au or the like by bonding. The second metal member 1 is branched in a mold area 6 into two central conductors 1a, 1b which extend out of the mold area 6. The first metal member 2 has two ground conductors 2a, 2b which are disposed one on each side of the central conductors 1a, 1b. If an existing semiconductor package has a lead pitch P and a lead width M, then the distance L.sub.
    Type: Grant
    Filed: November 18, 1994
    Date of Patent: February 27, 1996
    Assignee: NEC Corporation
    Inventor: Kazuyoshi Uemura
  • Patent number: 5446419
    Abstract: In a microwave oscillation apparatus including a negative resistance element, a microstrip line having a first end connected to the negative resistance element and a second end connected to a terminating resistor, and a dielectric resonator magnetically coupled to the microstrip line, a capacitive stub is provided on the microstrip line at a distance (1/4) .lambda..sub.s (2N-1) from the first end thereof, where .lambda..sub.s is a wavelength of a spurious oscillation frequency component and N is a positive integer.
    Type: Grant
    Filed: July 26, 1994
    Date of Patent: August 29, 1995
    Assignee: NEC Corporation
    Inventors: Tatsuya Miya, Kazuyoshi Uemura
  • Patent number: 5341111
    Abstract: A microwave oscillator circuit is provided for decreasing the number of passive elements such as inductance, etc. in microwave oscillators and frequency doublers. A microwave oscillator circuit is connected to a resonator circuit generating a signal at a frequency f, and produces at its output a signal of frequency nf, and comprises a first field effect transistor having a gate connected to the resonator circuit, a second field effect transistor whose source/drain path is connected in series with the source/drain path of the first field effect transistor and a connecting circuit for coupling either the gate or source of the first field effect transistor to the gate of the second field effect transistor. A signal of frequency nf is output at a node corresponding to a connection point between the source of the first field effect transistor and the drain of the second field effect transistor.
    Type: Grant
    Filed: September 16, 1992
    Date of Patent: August 23, 1994
    Assignee: NEC Corporation
    Inventors: Tatsuya Miya, Kazuyoshi Uemura, Sadayoshi Yoshida