Patents by Inventor Kazuyuki Arai
Kazuyuki Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11927923Abstract: A management apparatus in a time synchronization system includes a time variation information receiving unit configured to acquire time variation information and position information of a time synchronization apparatus, a position information classifying unit configured to classify time synchronization apparatuses into predetermined categories based on the acquired position information, a time variation analysis configured to determine majority based on whether patterns of time variation of the time synchronization apparatuses belonging to an identical category are identical to each other, and to analyze the time variation based on the determined results, and a filtering and delivery unit configured to output an instruction to block the time information received from the positioning satellite, to the time synchronization apparatus having abnormal time variation.Type: GrantFiled: March 5, 2019Date of Patent: March 12, 2024Assignee: Nippon Telegraph and Telephone CorporationInventors: Takaaki Hisashima, Hiroki Sakuma, Kaoru Arai, Ryuta Sugiyama, Shunichi Tsuboi, Osamu Kurokawa, Kazuyuki Matsumura
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Patent number: 10472723Abstract: Provided is a method of preventing reverse current flow through an ion exchange membrane electrolyzer, which method is capable of preventing a reverse current from being generated after stopping operation of the ion exchange membrane electrolyzer. A method of preventing reverse current flow through an ion exchange membrane electrolyzer 100, the ion exchange membrane electrolyzer 100 having an anode chamber 107 housing an anode, a cathode chamber 110 housing a cathode, an anode solution-supplying manifold 121 to feed anode solution to the anode chamber 107, and a cathode solution-supplying manifold 124 to feed cathode solution to the cathode chamber 110.Type: GrantFiled: January 6, 2015Date of Patent: November 12, 2019Assignee: THYSSENKRUPP UHDE CHLORINE ENGINEERS (JAPAN) LTD.Inventors: Kazuyuki Arai, Yoshinari Take, Terumi Hashimoto, Takaaki Matsuo, Toshikazu Hayashida
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Publication number: 20160194769Abstract: Provided is a method of preventing reverse current flow through an ion exchange membrane electrolyzer, which method is capable of preventing a reverse current from being generated after stopping operation of the ion exchange membrane electrolyzer. A method of preventing reverse current flow through an ion exchange membrane electrolyzer 100, the ion exchange membrane electrolyzer 100 having an anode chamber 107 housing an anode, a cathode chamber 110 housing a cathode, an anode solution-supplying manifold 121 to feed anode solution to the anode chamber 107, and a cathode solution-supplying manifold 124 to feed cathode solution to the cathode chamber 110.Type: ApplicationFiled: January 6, 2015Publication date: July 7, 2016Applicant: CHLORINE ENGINEERS CORP., LTD.Inventors: Kazuyuki ARAI, Yoshinari TAKE, Terumi HASHIMOTO, Takaaki MATSUO, Toshikazu HAYASHIDA
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Patent number: 9083367Abstract: An n-bit analog-to-digital converter includes a comparator that compares an analog input voltage with a comparison voltage; and a digital-to-analog converter that generates the comparison voltage in response to a result of the comparator, wherein the analog-to-digital converter outputs n-bit digital data corresponding to the analog input voltage, and wherein the analog-to-digital converter outputs a self-diagnosis result in such a way that the digital-to-analog converter generates a self-diagnosis voltage in response to the n-bit digital data and the comparator compares the analog input voltage with the self-diagnosis voltage.Type: GrantFiled: September 17, 2014Date of Patent: July 14, 2015Assignee: Renesas Electronics CorporationInventors: Kazuyuki Arai, Isao Sezaki
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Publication number: 20150002323Abstract: An n-bit analog-to-digital converter includes a comparator that compares an analog input voltage with a comparison voltage; and a digital-to-analog converter that generates the comparison voltage in response to a result of the comparator, wherein the analog-to-digital converter outputs n-bit digital data corresponding to the analog input voltage, and wherein the analog-to-digital converter outputs a self-diagnosis result in such a way that the digital-to-analog converter generates a self-diagnosis voltage in response to the n-bit digital data and the comparator compares the analog input voltage with the self-diagnosis voltage.Type: ApplicationFiled: September 17, 2014Publication date: January 1, 2015Inventors: Kazuyuki Arai, Isao Sezaki
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Patent number: 8866651Abstract: An analog-to-digital converter includes an input terminal to which an analog input voltage is input, a digital-to-analog converter unit, a comparator that compares the analog input voltage and an output voltage of the digital-to-analog converter unit with each other, a successive approximation register that stores a conversion result output from the comparator, a generator unit that generates added digital data and subtracted digital data, the added digital data and the subtracted digital data being obtained by adding and subtracting the conversion result to and from the conversion result retained by the successive approximation register, respectively, and a determination unit that determines whether or not a failure is occurring, by using a result of the comparison between the analog input voltage and output levels obtained by the digital-to-analog converter unit converting the added digital data and the subtracted digital data.Type: GrantFiled: October 30, 2013Date of Patent: October 21, 2014Assignee: Renesas Electronics CorporationInventors: Kazuyuki Arai, Isao Sezaki
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Publication number: 20140118174Abstract: An analog-to-digital converter includes an input terminal to which an analog input voltage is input, a digital-to-analog converter unit, a comparator that compares the analog input voltage and an output voltage of the digital-to-analog converter unit with each other, a successive approximation register that stores a conversion result output from the comparator, a generator unit that generates added digital data and subtracted digital data, the added digital data and the subtracted digital data being obtained by adding and subtracting the conversion result to and from the conversion result retained by the successive approximation register, respectively, and a determination unit that determines whether or not a failure is occurring, by using a result of the comparison between the analog input voltage and output levels obtained by the digital-to-analog converter unit converting the added digital data and the subtracted digital data.Type: ApplicationFiled: October 30, 2013Publication date: May 1, 2014Applicant: Renesas Electronics CorporationInventors: Kazuyuki Arai, Isao Sezaki
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Patent number: 6852998Abstract: A source line is directly connected to a source terminal composed of indium zinc oxide in a thin-film transistor substrate. A gate line is directly connected to a gate terminal composed of indium zinc oxide. Alternatively, drain electrodes of thin-film transistors for switching a plurality of pixel electrodes are directly connected to pixel electrodes composed of indium zinc oxide. These configurations do not require a passivation film which is essential for conventional thin-film transistor substrates, and the resulting thin-film transistor substrate can be made by a reduced number of manufacturing steps.Type: GrantFiled: March 7, 2003Date of Patent: February 8, 2005Assignee: LG Philips LCD Co., Ltd.Inventors: Chae Gee Sung, Jo Gyoo Chul, Makoto Sasaki, Kazuyuki Arai
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Patent number: 6649936Abstract: A source line is directly connected to a source terminal composed of indium zinc oxide in a thin-film transistor substrate. A gate line is directly connected to a gate terminal composed of indium zinc oxide. Alternatively, drain electrodes of thin-film transistors for switching a plurality of pixel electrodes are directly connected to pixel electrodes composed of indium zinc oxide. These configurations do not require a passivation film which is essential for conventional thin-film transistor substrates, and the resulting thin-film transistor substrate can be made by a reduced number of manufacturing steps.Type: GrantFiled: March 15, 2000Date of Patent: November 18, 2003Assignee: LG. Philips LCD Co., Ltd.Inventors: Chae Gee Sung, Jo Gyoo Chul, Makoto Sasaki, Kazuyuki Arai
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Publication number: 20030164498Abstract: A source line is directly connected to a source terminal composed of indium zinc oxide in a thin-film transistor substrate. A gate line is directly connected to a gate terminal composed of indium zinc oxide. Alternatively, drain electrodes of thin-film transistors for switching a plurality of pixel electrodes are directly connected to pixel electrodes composed of indium zinc oxide. These configurations do not require a passivation film which is essential for conventional thin-film transistor substrates, and the resulting thin-film transistor substrate can be made by a reduced number of manufacturing steps.Type: ApplicationFiled: March 7, 2003Publication date: September 4, 2003Inventors: Chae Gee Sung, Jo Gyoo Chul, Makoto Sasaki, Kazuyuki Arai
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Patent number: 6533965Abstract: A transparent electrically conductive oxide film is composed of a compound oxide containing indium oxide, tin oxide, and zinc oxide and includes a connecting section, in which the tin content is higher than the zinc content at least in connecting section, and at least the connection section has crystallinity. Alternatively, in the transparent electrically conductive oxide film, the atomic percentage of zinc to the total of zinc, indium, and tin is in the range of about 1 at % through about 9 at %, the atomic ratio of tin to zinc is about 1 or more, the atomic percentage of tin to the total of zinc, indium, and tin is about 20 at % or less, and at least a portion thereof has crystallinity.Type: GrantFiled: November 22, 2000Date of Patent: March 18, 2003Assignees: Alps Electric Co., LTD, LG. Philips LCD Co., Ltd.Inventors: Makoto Sasaki, Chae Gee Sung, Kazuyuki Arai
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Patent number: 5682687Abstract: Stretchable shoes capable of being fixed without causing any stretch of the shoes once adjustment of a size thereof depending on a wearer is completed. Velcro-type hook and loop fasteners are arranged on a heel, so that a size of the shoes may be kept fixed once adjustment of the size is carried out, because engagement between the fasteners exhibits rigidity to a degree sufficient to substantially prevent release of the engagement. Also, the stretchable shoes permit adjustment of a size of the shoes to be readily accomplished by merely loosening a single countersunk screw kept tightened.Type: GrantFiled: May 23, 1995Date of Patent: November 4, 1997Inventor: Kazuyuki Arai
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Patent number: 5311164Abstract: A MELF (Metal Electrode Face Bonding Device) surge absorbing element which can be connected across a pair of input lines of an electronic device. The surge absorbing element is secured in electrical contact with the input lines by a conductive heat releasable adhering means, e.g., a solder. A spring is positioned in biased relationship against the surge absorbing element. When the surge absorbing element is subjected to overvoltages or overcurrents continuously across the input lines, the surge absorbing element heats up, which, in turn, heats the adhering means. When the temperature reaches a predetermined value, the adhering means releases its securement of the surge absorbing element, e.g., the solder melts, and no longer holds the element. When this occurs, the bias of the spring means positioned against the now unsecured surge absorbing element serves to move the element away from and out of electrical contact with the adhering means and, in turn, the input lines.Type: GrantFiled: October 8, 1992Date of Patent: May 10, 1994Assignee: Mitsubishi Materials CorporationInventors: Fujio Ikeda, Kazuyuki Arai
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Patent number: 5198791Abstract: The surge absorber having a surge absorbing element, and first and second wire means for electrically connecting the surge absorbing element across the input lines of an electronic device. The first and second wire means are connected to the surge absorber by conductive heat releasable means, for example, a low melting point solder. The second wire means includes a spring loaded member such that, on release of the first or second wire means by the first or second heat releasable means, respectively, by melting of the solder due to heat generated by the surge absorbing element, the surge absorbing element moves away from the first or second wire means. The surge absorber prevents an abnormal heating of the surge absorbing element when continuous overvoltages or overcurrents pass therethrough.Type: GrantFiled: February 3, 1992Date of Patent: March 30, 1993Assignee: Mitsubishi Materials CorporationInventors: Takashi Shibayama, Kazuyuki Arai, Fujio Ikeda