Patents by Inventor Kazuyuki Arai

Kazuyuki Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11927923
    Abstract: A management apparatus in a time synchronization system includes a time variation information receiving unit configured to acquire time variation information and position information of a time synchronization apparatus, a position information classifying unit configured to classify time synchronization apparatuses into predetermined categories based on the acquired position information, a time variation analysis configured to determine majority based on whether patterns of time variation of the time synchronization apparatuses belonging to an identical category are identical to each other, and to analyze the time variation based on the determined results, and a filtering and delivery unit configured to output an instruction to block the time information received from the positioning satellite, to the time synchronization apparatus having abnormal time variation.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: March 12, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Takaaki Hisashima, Hiroki Sakuma, Kaoru Arai, Ryuta Sugiyama, Shunichi Tsuboi, Osamu Kurokawa, Kazuyuki Matsumura
  • Patent number: 10472723
    Abstract: Provided is a method of preventing reverse current flow through an ion exchange membrane electrolyzer, which method is capable of preventing a reverse current from being generated after stopping operation of the ion exchange membrane electrolyzer. A method of preventing reverse current flow through an ion exchange membrane electrolyzer 100, the ion exchange membrane electrolyzer 100 having an anode chamber 107 housing an anode, a cathode chamber 110 housing a cathode, an anode solution-supplying manifold 121 to feed anode solution to the anode chamber 107, and a cathode solution-supplying manifold 124 to feed cathode solution to the cathode chamber 110.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: November 12, 2019
    Assignee: THYSSENKRUPP UHDE CHLORINE ENGINEERS (JAPAN) LTD.
    Inventors: Kazuyuki Arai, Yoshinari Take, Terumi Hashimoto, Takaaki Matsuo, Toshikazu Hayashida
  • Publication number: 20160194769
    Abstract: Provided is a method of preventing reverse current flow through an ion exchange membrane electrolyzer, which method is capable of preventing a reverse current from being generated after stopping operation of the ion exchange membrane electrolyzer. A method of preventing reverse current flow through an ion exchange membrane electrolyzer 100, the ion exchange membrane electrolyzer 100 having an anode chamber 107 housing an anode, a cathode chamber 110 housing a cathode, an anode solution-supplying manifold 121 to feed anode solution to the anode chamber 107, and a cathode solution-supplying manifold 124 to feed cathode solution to the cathode chamber 110.
    Type: Application
    Filed: January 6, 2015
    Publication date: July 7, 2016
    Applicant: CHLORINE ENGINEERS CORP., LTD.
    Inventors: Kazuyuki ARAI, Yoshinari TAKE, Terumi HASHIMOTO, Takaaki MATSUO, Toshikazu HAYASHIDA
  • Patent number: 9083367
    Abstract: An n-bit analog-to-digital converter includes a comparator that compares an analog input voltage with a comparison voltage; and a digital-to-analog converter that generates the comparison voltage in response to a result of the comparator, wherein the analog-to-digital converter outputs n-bit digital data corresponding to the analog input voltage, and wherein the analog-to-digital converter outputs a self-diagnosis result in such a way that the digital-to-analog converter generates a self-diagnosis voltage in response to the n-bit digital data and the comparator compares the analog input voltage with the self-diagnosis voltage.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: July 14, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyuki Arai, Isao Sezaki
  • Publication number: 20150002323
    Abstract: An n-bit analog-to-digital converter includes a comparator that compares an analog input voltage with a comparison voltage; and a digital-to-analog converter that generates the comparison voltage in response to a result of the comparator, wherein the analog-to-digital converter outputs n-bit digital data corresponding to the analog input voltage, and wherein the analog-to-digital converter outputs a self-diagnosis result in such a way that the digital-to-analog converter generates a self-diagnosis voltage in response to the n-bit digital data and the comparator compares the analog input voltage with the self-diagnosis voltage.
    Type: Application
    Filed: September 17, 2014
    Publication date: January 1, 2015
    Inventors: Kazuyuki Arai, Isao Sezaki
  • Patent number: 8866651
    Abstract: An analog-to-digital converter includes an input terminal to which an analog input voltage is input, a digital-to-analog converter unit, a comparator that compares the analog input voltage and an output voltage of the digital-to-analog converter unit with each other, a successive approximation register that stores a conversion result output from the comparator, a generator unit that generates added digital data and subtracted digital data, the added digital data and the subtracted digital data being obtained by adding and subtracting the conversion result to and from the conversion result retained by the successive approximation register, respectively, and a determination unit that determines whether or not a failure is occurring, by using a result of the comparison between the analog input voltage and output levels obtained by the digital-to-analog converter unit converting the added digital data and the subtracted digital data.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: October 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyuki Arai, Isao Sezaki
  • Publication number: 20140118174
    Abstract: An analog-to-digital converter includes an input terminal to which an analog input voltage is input, a digital-to-analog converter unit, a comparator that compares the analog input voltage and an output voltage of the digital-to-analog converter unit with each other, a successive approximation register that stores a conversion result output from the comparator, a generator unit that generates added digital data and subtracted digital data, the added digital data and the subtracted digital data being obtained by adding and subtracting the conversion result to and from the conversion result retained by the successive approximation register, respectively, and a determination unit that determines whether or not a failure is occurring, by using a result of the comparison between the analog input voltage and output levels obtained by the digital-to-analog converter unit converting the added digital data and the subtracted digital data.
    Type: Application
    Filed: October 30, 2013
    Publication date: May 1, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Kazuyuki Arai, Isao Sezaki
  • Patent number: 6852998
    Abstract: A source line is directly connected to a source terminal composed of indium zinc oxide in a thin-film transistor substrate. A gate line is directly connected to a gate terminal composed of indium zinc oxide. Alternatively, drain electrodes of thin-film transistors for switching a plurality of pixel electrodes are directly connected to pixel electrodes composed of indium zinc oxide. These configurations do not require a passivation film which is essential for conventional thin-film transistor substrates, and the resulting thin-film transistor substrate can be made by a reduced number of manufacturing steps.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: February 8, 2005
    Assignee: LG Philips LCD Co., Ltd.
    Inventors: Chae Gee Sung, Jo Gyoo Chul, Makoto Sasaki, Kazuyuki Arai
  • Patent number: 6649936
    Abstract: A source line is directly connected to a source terminal composed of indium zinc oxide in a thin-film transistor substrate. A gate line is directly connected to a gate terminal composed of indium zinc oxide. Alternatively, drain electrodes of thin-film transistors for switching a plurality of pixel electrodes are directly connected to pixel electrodes composed of indium zinc oxide. These configurations do not require a passivation film which is essential for conventional thin-film transistor substrates, and the resulting thin-film transistor substrate can be made by a reduced number of manufacturing steps.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: November 18, 2003
    Assignee: LG. Philips LCD Co., Ltd.
    Inventors: Chae Gee Sung, Jo Gyoo Chul, Makoto Sasaki, Kazuyuki Arai
  • Publication number: 20030164498
    Abstract: A source line is directly connected to a source terminal composed of indium zinc oxide in a thin-film transistor substrate. A gate line is directly connected to a gate terminal composed of indium zinc oxide. Alternatively, drain electrodes of thin-film transistors for switching a plurality of pixel electrodes are directly connected to pixel electrodes composed of indium zinc oxide. These configurations do not require a passivation film which is essential for conventional thin-film transistor substrates, and the resulting thin-film transistor substrate can be made by a reduced number of manufacturing steps.
    Type: Application
    Filed: March 7, 2003
    Publication date: September 4, 2003
    Inventors: Chae Gee Sung, Jo Gyoo Chul, Makoto Sasaki, Kazuyuki Arai
  • Patent number: 6533965
    Abstract: A transparent electrically conductive oxide film is composed of a compound oxide containing indium oxide, tin oxide, and zinc oxide and includes a connecting section, in which the tin content is higher than the zinc content at least in connecting section, and at least the connection section has crystallinity. Alternatively, in the transparent electrically conductive oxide film, the atomic percentage of zinc to the total of zinc, indium, and tin is in the range of about 1 at % through about 9 at %, the atomic ratio of tin to zinc is about 1 or more, the atomic percentage of tin to the total of zinc, indium, and tin is about 20 at % or less, and at least a portion thereof has crystallinity.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: March 18, 2003
    Assignees: Alps Electric Co., LTD, LG. Philips LCD Co., Ltd.
    Inventors: Makoto Sasaki, Chae Gee Sung, Kazuyuki Arai
  • Patent number: 5682687
    Abstract: Stretchable shoes capable of being fixed without causing any stretch of the shoes once adjustment of a size thereof depending on a wearer is completed. Velcro-type hook and loop fasteners are arranged on a heel, so that a size of the shoes may be kept fixed once adjustment of the size is carried out, because engagement between the fasteners exhibits rigidity to a degree sufficient to substantially prevent release of the engagement. Also, the stretchable shoes permit adjustment of a size of the shoes to be readily accomplished by merely loosening a single countersunk screw kept tightened.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: November 4, 1997
    Inventor: Kazuyuki Arai
  • Patent number: 5311164
    Abstract: A MELF (Metal Electrode Face Bonding Device) surge absorbing element which can be connected across a pair of input lines of an electronic device. The surge absorbing element is secured in electrical contact with the input lines by a conductive heat releasable adhering means, e.g., a solder. A spring is positioned in biased relationship against the surge absorbing element. When the surge absorbing element is subjected to overvoltages or overcurrents continuously across the input lines, the surge absorbing element heats up, which, in turn, heats the adhering means. When the temperature reaches a predetermined value, the adhering means releases its securement of the surge absorbing element, e.g., the solder melts, and no longer holds the element. When this occurs, the bias of the spring means positioned against the now unsecured surge absorbing element serves to move the element away from and out of electrical contact with the adhering means and, in turn, the input lines.
    Type: Grant
    Filed: October 8, 1992
    Date of Patent: May 10, 1994
    Assignee: Mitsubishi Materials Corporation
    Inventors: Fujio Ikeda, Kazuyuki Arai
  • Patent number: 5198791
    Abstract: The surge absorber having a surge absorbing element, and first and second wire means for electrically connecting the surge absorbing element across the input lines of an electronic device. The first and second wire means are connected to the surge absorber by conductive heat releasable means, for example, a low melting point solder. The second wire means includes a spring loaded member such that, on release of the first or second wire means by the first or second heat releasable means, respectively, by melting of the solder due to heat generated by the surge absorbing element, the surge absorbing element moves away from the first or second wire means. The surge absorber prevents an abnormal heating of the surge absorbing element when continuous overvoltages or overcurrents pass therethrough.
    Type: Grant
    Filed: February 3, 1992
    Date of Patent: March 30, 1993
    Assignee: Mitsubishi Materials Corporation
    Inventors: Takashi Shibayama, Kazuyuki Arai, Fujio Ikeda