Patents by Inventor Kazuyuki Hori

Kazuyuki Hori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9031144
    Abstract: To satisfy the required SNR values for each system and/or each channel, a peak factor reduction device for reducing peak components included in a transmission signal, generates a cancellation signal to be multiplexed on the transmission signal, and the peak factor reduction device changes an amplitude of the generated cancellation signal according to a signal noise ratio required for the transmission signal and a power level of the transmission signal.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: May 12, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Kazuyuki Hori, Yuuji Ishida, Qian He
  • Publication number: 20140254718
    Abstract: To satisfy the required SNR values for each system and/or each channel, it is provided a peak factor reduction device for reducing peak components included in a transmission signal, wherein the peak factor reduction device generates a cancellation signal to be multiplexed on the transmission signal, and the peak factor reduction device changes an amplitude of the generated cancellation signal according to a signal noise ratio required for the transmission signal and a power level of the transmission signal.
    Type: Application
    Filed: February 26, 2014
    Publication date: September 11, 2014
    Applicant: HITACHI, LTD.
    Inventors: Kazuyuki HORI, Yuuji ISHIDA, Qian HE
  • Patent number: 8315338
    Abstract: To detect phase mismatches between in-phase and quadrature signals of a quadrature demodulator. The phase mismatches can be detected using the signals obtained by removing high frequency components of output of a multiplier by a low pass filter, the output being the product of the in-phase signals of which low frequency components are removed by a first high pass filter by the quadrature signals of which low frequency components are removed by a second high pass filter.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: November 20, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Shigenori Hayase, Kazuyuki Hori
  • Patent number: 8280442
    Abstract: Even if a receiver has a normal gain and a lowered intermodulation distortion characteristics, a fault detection is possible. A test signal transmitter sends a test signal having at least two frequencies to a radio receiver through a coupler. A digital signal processing section receives a signal which includes an IM3 component generated by the radio receiver and measures the electric power of fundamental wave components and the IM3 component. Then, the digital signal processing section calculates the gain of the radio receiver and IIP3, which is an index for intermodulation distortion characteristics, of the radio receiver 207 from the calculated electric power. A base station control section determines whether the gain and IIP3 of the radio receiver fall in predetermined ranges to determine whether the radio receiver works normally or has a fault.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: October 2, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Haruo Nakano, Kazuyuki Hori, Masanori Taira, Takahiro Chiba, Yasuyuki Magara
  • Patent number: 8175198
    Abstract: A matched filter and receiver is provided to delete the tap coefficients of a matched filter used in an OFDM receiver. In the matched filter and receiver, a transmitting signal is generated by using a symmetric series (Y) obtained from C[k]=exp[j*?*M/N*(k+0.5)^2], where X=[0, C[N/2], C[N/2+1], . . . , C[N?1], 0, 0, . . . , 0, C[0], C[1], . . . , C[N/2?1]], and Y=inverse FFT (X) as a base symbol. The matched filter, which detects the signal, reduces the number of multipliers by using the coefficient symmetric property.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: May 8, 2012
    Assignee: Hitachi, Ltd.
    Inventor: Kazuyuki Hori
  • Patent number: 8140106
    Abstract: The function of comparing power of a signal obtained by multiplying an input signal by an EVM target value and power of a peak suppression signal, and automatically adjusting a peak factor threshold value Vt in such a manner that the values of both power become equal to each other, is added to the peak factor reduction device. The peak factor reduction device is also added with the function of comparing instantaneous amplitude values of a signal Sout after a peak factor reduction and the peak factor threshold value Vt, and automatically calculating a peak detection width N so as to suppress the residual of each peak.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: March 20, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Takahiro Chiba, Masanori Taira, Kazuyuki Hori
  • Patent number: 7995674
    Abstract: There is a need for effectively compensating distortion when a predistortion transmitter is subject to not only a memory effect due to nonlinearity of an amplifier, but also a modulator's DC offset, IQ unbalance, or local quadrature error. A predistortor to be used is a polynomial predistortor including a polynomial basis generation portion and an inner product calculation portion. The polynomial basis generation portion delays a real part and an imaginary part of a complex input signal Sx=Ix+jQx for up to M samples to generate 2(M+1) signals, duplicately combines these signals to generate monomials having maximum degree N, and outputs, as a basis vector, all or part of the monomials depending or needs. The inner product calculation portion performs an inner product calculation using a coefficient vector, i.e., a set of complex numbers sized equally to the basis vector to find a polynomial value and outputs the value as a complex signal.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: August 9, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Kazuyuki Hori, Shouhei Murakami, Yuji Ishida, Tomoya Uchiike, Yoshiaki Hasegawa
  • Publication number: 20110158353
    Abstract: To detect phase mismatches between in-phase and quadrature signals of a quadrature demodulator. The phase mismatches can be detected using the signals obtained by removing high frequency components of output of a multiplier by a low pass filter, the output being the product of the in-phase signals of which low frequency components are removed by a first high pass filter by the quadrature signals of which low frequency components are removed by a second high pass filter.
    Type: Application
    Filed: March 8, 2011
    Publication date: June 30, 2011
    Inventors: Shigenori HAYASE, Kazuyuki Hori
  • Patent number: 7941476
    Abstract: An object of this invention is to provide a method of designing a complex transfer function which can be realized in a passive RC complex filter at the same time while perfectly succeeding to features of a prototype lowpass characteristic. In this invention, as a first step, a prototype lowpass characteristic F(p) having a pole on a unit circle is designed. Next, as a second step, a bilinear variable transformation expressed by p=j(s?j)/(s+j) is performed with respect to the prototype characteristic F(p) to derive a complex coefficient transfer function G(s). As a third step, a passive RC complex filter H(s) is designed based upon the complex coefficient transfer function G(s).
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: May 10, 2011
    Assignee: Hitachi, Ltd.
    Inventor: Kazuyuki Hori
  • Publication number: 20110096865
    Abstract: There is a need for effectively compensating distortion when a predistortion transmitter is subject to not only a memory effect due to nonlinearity of an amplifier, but also a modulator's DC offset, IQ unbalance, or local quadrature error. A predistortor to be used is a polynomial predistortor including a polynomial basis generation portion and an inner product calculation portion. The polynomial basis generation portion delays a real part and an imaginary part of a complex input signal Sx=Ix+jQx for up to M samples to generate 2(M+1) signals, duplicately combines these signals to generate monomials having maximum degree N, and outputs, as a basis vector, all or part of the monomials depending or needs. The inner product calculation portion performs an inner product calculation using a coefficient vector, i.e., a set of complex numbers sized equally to the basis vector to find a polynomial value and outputs the value as a complex signal.
    Type: Application
    Filed: December 29, 2010
    Publication date: April 28, 2011
    Inventors: Kazuyuki Hori, Shouhei Murakami, Yuji Ishida, Tomoya Uchiike, Yoshiaki Hasegawa
  • Patent number: 7933569
    Abstract: A wireless communication device including: a transmitter including two DA converter units which convert two digital signals into analog signals; a combiner which combines the analog signals; a distributor which extracts a portion of the combined signal as a feedback signal; an AD converter which converts the feedback signal; an oscillator unit which supplies clock signals to operate the DA converter units and the AD converter; a first separation unit which separates the feedback signal converted by the AD converter into two signals; and a comparator unit which compares at least one of the two digital signals that are obtained by separating the inputted digital signal, or, at least one of the two digital signals that are separately inputted, with the feedback signal separated by the first separation unit, wherein the oscillator unit controls the output clock signals based on a result of the comparison by the comparator unit.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: April 26, 2011
    Assignee: Hitachi, Ltd.
    Inventors: May Suzuki, Kazuyuki Hori, Takashi Yano
  • Patent number: 7920652
    Abstract: To detect phase mismatches between in-phase and quadrature signals of a quadrature demodulator. The phase mismatches can be detected using the signals obtained by removing high frequency components of output of a multiplier by a low pass filter, the output being the product of the in-phase signals of which low frequency components are removed by a first high pass filter by the quadrature signals of which low frequency components are removed by a second high pass filter.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: April 5, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Shigenori Hayase, Kazuyuki Hori
  • Publication number: 20110009153
    Abstract: The function of comparing power of a signal obtained by multiplying an input signal by an EVM target value and power of a peak suppression signal, and automatically adjusting a peak factor threshold value Vt in such a manner that the values of both power become equal to each other, is added to the peak factor reduction device. The peak factor reduction device is also added with the function of comparing instantaneous amplitude values of a signal Sout after a peak factor reduction and the peak factor threshold value Vt, and automatically calculating a peak detection width N so as to suppress the residual of each peak.
    Type: Application
    Filed: June 28, 2010
    Publication date: January 13, 2011
    Applicant: HITACHI, LTD.
    Inventors: Takahiro CHIBA, Masanori TAIRA, Kazuyuki HORI
  • Patent number: 7864881
    Abstract: There is a need for effectively compensating distortion when a predistortion transmitter is subject to not only a memory effect due to nonlinearity of an amplifier, but also a modulator's DC offset, IQ unbalance, or local quadrature error. A predistortor to be used is a polynomial predistortor including a polynomial basis generation portion and an inner product calculation portion. The polynomial basis generation portion delays a real part and an imaginary part of a complex input signal Sx=Ix+jQx for up to M samples to generate 2(M+1) signals, duplicately combines these signals to generate monomials having maximum degree N, and outputs, as a basis vector, all or part of the monomials depending or needs. The inner product calculation portion performs an inner product calculation using a coefficient vector, i.e., a set of complex numbers sized equally to the basis vector to find a polynomial value and outputs the value as a complex signal.
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: January 4, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Kazuyuki Hori, Shouhei Murakami, Yuji Ishida, Tomoya Uchiike, Yoshiaki Hasegawa
  • Patent number: 7817746
    Abstract: A peak factor reduction unit that never allow peak factor reproduction even when interpolation is done in a succeeding stage. The unit detects a local maximum value of amplitude components from an input complex signal and supplies a complex signal that passes a band limiting baseband filter and an interpolation filter to a correction signal generation unit for generating a correction signal used for peak factor reduction and reduces a peak factor of the input complex signal with use of the correction signal generated from an interpolated complex signal.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: October 19, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Kazuyuki Hori, Hideaki Arai, Shouhei Murakami
  • Patent number: 7809078
    Abstract: An OFDM modulator having a peak factor reduction function. The OFDM modulator has a peak factor reduction unit between an IFFT unit and a guard interval insertion unit thereof. The peak factor reduction unit converts a complex signal X1 outputted from the IFFT unit into a complex signal X2 with a reduced peak factor based on subcarrier map information. The peak factor reduction unit generates a peak factor reduction signal by a linear combination of complex exponential functions that correspond to subcarrier frequencies to be used for wave transmission, as bases. The peak factor reduction signal is derived by repetition of, for example, a weighted least squares method or convolution processing by a fast Fourier transform.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: October 5, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Kazuyuki Hori, Yuji Ishida, Shouhei Murakami, Kenji Yanagi
  • Patent number: 7800452
    Abstract: The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: September 21, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Manabu Kawabe, Kazuyuki Hori, Satoshi Tanaka, Yukinori Akamine, Masumi Kasahara, Kazuo Watanabe
  • Publication number: 20100075709
    Abstract: Even if a receiver has a normal gain and a lowered intermodulation distortion characteristics, a fault detection is possible. A test signal transmitter sends a test signal having at least two frequencies to a radio receiver through a coupler. A digital signal processing section receives a signal which includes an IM3 component generated by the radio receiver and measures the electric power of fundamental wave components and the IM3 component. Then, the digital signal processing section calculates the gain of the radio receiver and IIP3, which is an index for intermodulation distortion characteristics, of the radio receiver 207 from the calculated electric power. A base station control section determines whether the gain and IIP3 of the radio receiver fall in predetermined ranges to determine whether the radio receiver works normally or has a fault.
    Type: Application
    Filed: June 16, 2009
    Publication date: March 25, 2010
    Inventors: Haruo NAKANO, Kazuyuki Hori, Masanori Taira, Takahiro Chiba, Yasuyuki Magara
  • Publication number: 20090263509
    Abstract: The problems to be solved by the invention are to provide antibacterial agents originated from natural products that are safe for regular use with potent antibacterial activity, and antibacterial compositions containing said antibacterial agents. Antibacterial agents containing Eysenhardtia adenostylis extract or isoflavan compounds are a solution to the problem. Also antibacterial agents containing Eysenhardtia adenostylis extract or isoflavan compounds as active ingredients. The antibacterial agents can be applied to products such as cosmetics, including quasi-drugs, pharmaceuticals and foods. Further, antibacterial compositions containing these antibacterial agents, Eysenhardtia adenostylis extract or isoflavan compounds, and other compositions such as cosmetics, including quasi-drugs, pharmaceuticals and foods.
    Type: Application
    Filed: February 25, 2005
    Publication date: October 22, 2009
    Applicant: SAKAMOTO BIO CO., LTD
    Inventors: Kenji Sakamoto, Toshiyuki Mukaiyama, Kazuyuki Hori, Saori Takahashi
  • Publication number: 20090175391
    Abstract: A matched filter and receiver is provided to delete the tap coefficients of a matched filter used in an OFDM receiver. In the matched filter and receiver, a transmitting signal is generated by using a symmetric series (Y) obtained from C[k]=exp [j*?*M/N*(k+0.5)?2], where X=[0, C[N/2], C[N/2+1], . . . , C[N?1], 0, 0, . . . , 0, C[0], C[1], . . . , C[N/2?1]], and Y=inverse FFT (X) as a base symbol. The matched filter, which detects the signal, reduces the number of multipliers by using the coefficient symmetric property.
    Type: Application
    Filed: December 18, 2008
    Publication date: July 9, 2009
    Inventor: Kazuyuki HORI