Patents by Inventor Kazuyuki Hozawa

Kazuyuki Hozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230290896
    Abstract: An semiconductor detector includes an n-type semiconductor substrate, a detection electrode formed on a first surface of the semiconductor substrate, a plurality of drift electrodes formed to surround the detection electrode and applied with a voltage causing a potential gradient in which a potential changes toward the detection electrode, a radiation incidence window provided on a second surface of the semiconductor substrate, a P-type semiconductor region formed by adding boron to a surface side on the second surface of the semiconductor substrate through the radiation incidence window, and a depleting electrode causing a reverse bias between the P-type semiconductor region formed on the second surface and an N-type semiconductor region formed in the semiconductor substrate. F is added to the P-type semiconductor region, and a region with the highest concentration of F is located deeper than a region with the highest concentration of B.
    Type: Application
    Filed: January 6, 2023
    Publication date: September 14, 2023
    Inventors: Kazuyuki HOZAWA, Takashi Takahama
  • Patent number: 11417702
    Abstract: A technique capable of improving a performance of a semiconductor detector is provided. The semiconductor detector is made based on injection of an underfill into a gap between a first semiconductor chip and a second semiconductor chip in a flip-chip connection state, but the underfill is not formed in periphery of a connection structure connecting a reading electrode pad and a gate terminal through a bump electrode.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: August 16, 2022
    Assignee: HITACHI, LTD.
    Inventors: Kazuyuki Hozawa, Taiichi Takezaki
  • Publication number: 20210375978
    Abstract: A technique capable of improving a performance of a semiconductor detector is provided. The semiconductor detector is made based on injection of an underfill into a gap between a first semiconductor chip and a second semiconductor chip in a flip-chip connection state, but the underfill is not formed in periphery of a connection structure connecting a reading electrode pad and a gate terminal through a bump electrode.
    Type: Application
    Filed: March 19, 2021
    Publication date: December 2, 2021
    Inventors: Kazuyuki Hozawa, Taiichi Takezaki
  • Publication number: 20190324160
    Abstract: An X-ray detector and an X-ray measurement device capable of improving detection efficiency of an X-ray while maintaining high resolution are provided. An X-ray detector includes: a first SDD chip that detects a fluorescent X-ray generated from a sample with a first energy sensitivity; a second SDD chip that detects the fluorescent X-ray with a second energy sensitivity different from the first energy sensitivity; a first signal line electrically connected to the first SDD chip; and a second signal line electrically connected to the second SDD chip. The X-ray detector further includes an amplifier that is electrically connected to the first signal line and the second signal line and amplifies a signal.
    Type: Application
    Filed: November 21, 2018
    Publication date: October 24, 2019
    Applicant: HITACHI, LTD.
    Inventors: Kazuyuki HOZAWA, Takashi TAKAHAMA
  • Publication number: 20160300764
    Abstract: A piece of first connecting wiring 210 is formed of a lower layer wiring close to a semiconductor element. A piece of second connecting wiring 220 is formed of an upper layer wiring far from the semiconductor element. A first opening that passes through a silicon substrate 100 and reaches the piece of first connecting wiring 210 and a second opening that passes through the silicon substrate 100 and reaches the piece of second connecting wiring 220 are formed from a back surface of the silicon substrate 100. After that, a first through silicon via 230 and a second through silicon via 240 are formed inside the first opening and the second opening, respectively. Accordingly, the first through silicon via 230 for propagating a signal, to be coupled to the piece of first connecting wiring 210, and the second through silicon via 240 for supplying a clock and a power source, to be coupled to the piece of second connecting wiring 220, can be formed.
    Type: Application
    Filed: July 5, 2013
    Publication date: October 13, 2016
    Inventors: Kenichi TAKEDA, Mayu AOKI, Kazuyuki HOZAWA
  • Patent number: 9153495
    Abstract: A method of manufacturing a semiconductor device includes: a step of forming an inorganic insulating film and an organic insulating film on one surface of a first substrate; a step of forming an opening portion by dry-etching a laminated film of them; a step of forming a bump electrode inside the opening portion; and a step (bonding step) of bonding the one surface of the first substrate having a bump electrode formed thereon and one surface of a second substrate having a bump electrode formed thereon to each other. A surface treatment on the inorganic insulating film is performed subsequent to the step of forming the opening portion but prior to the bonding step. By performing the surface treatment on the organic insulating film, connecting property between the substrates can be improved.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: October 6, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Mayu Aoki, Kenichi Takeda, Kazuyuki Hozawa
  • Publication number: 20150187651
    Abstract: A method of manufacturing a semiconductor device includes: a step of forming an inorganic insulating film and an organic insulating film on one surface of a first substrate; a step of forming an opening portion by dry-etching a laminated film of them; a step of forming a bump electrode inside the opening portion; and a step (bonding step) of bonding the one surface of the first substrate having a bump electrode formed thereon and one surface of a second substrate having a bump electrode formed thereon to each other. A surface treatment on the inorganic insulating film is performed subsequent to the step of forming the opening portion but prior to the bonding step. By performing the surface treatment on the organic insulating film, connecting property between the substrates can be improved.
    Type: Application
    Filed: March 4, 2015
    Publication date: July 2, 2015
    Inventors: Mayu Aoki, Kenichi Takeda, Kazuyuki Hozawa
  • Patent number: 8749028
    Abstract: When a silicon through electrode is to be formed from a back surface (the surface on which a semiconductor device is not formed) of a silicon substrate, a wide range of an interlayer insulating film made of a Low-k material absorbs moisture, and there is a problem that the electrical characteristics of wiring are degraded. The above-described problem can be solved by forming at least a single ring-shaped frame laid out to enclose the silicon through electrode by using metal wirings in plural layers and a connection via connecting the upper and lower metal wirings in a Low-k material layer penetrated by the silicon through electrode and by forming a moisture barrier film made up of at least a metal wiring and a connection via between the silicon through electrode and a circuit wiring formed in the vicinity of the silicon through electrode.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: June 10, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Mayu Aoki, Kenichi Takeda, Kazuyuki Hozawa
  • Patent number: 8618667
    Abstract: A bump electrode, a dummy bump, and a heat-resistant polymer film, whose upper-surface heights are uniformed, are formed on each of a first silicon substrate and a second silicon substrate, and then, the first silicon substrate and the second silicon substrate are bonded to each other so that the bump electrodes formed on the respective substrates are electrically connected to each other. At this time, the dummy bump is arranged so as to be bonded to the heat-resistant polymer film on the silicon substrate opposed thereto, so that a semiconductor device having both of good electrical connection between the bump electrodes and bump protection performance obtained by a polymer film with high heat resistance and without voids can be achieved.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: December 31, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Kenichi Takeda, Mayu Aoki, Kazuyuki Hozawa
  • Publication number: 20130285253
    Abstract: A method of manufacturing a semiconductor device includes: a step of forming an inorganic insulating film and an organic insulating film on one surface of a first substrate; a step of forming an opening portion by dry-etching a laminated film of them; a step of forming a bump electrode inside the opening portion; and a step (bonding step) of bonding the one surface of the first substrate having a bump electrode formed thereon and one surface of a second substrate having a bump electrode formed thereon to each other. A surface treatment on the inorganic insulating film is performed subsequent to the step of forming the opening portion but prior to the bonding step. By performing the surface treatment on the organic insulating film, connecting property between the substrates can be improved.
    Type: Application
    Filed: March 15, 2013
    Publication date: October 31, 2013
    Applicant: HITACHI, LTD.
    Inventors: Mayu Aoki, Kenichi Takeda, Kazuyuki Hozawa
  • Patent number: 8410615
    Abstract: A semiconductor device including two silicon wafers stacked and bonded together with bumps of one wafer electrically coupled with those of the other wafer, in which generation of voids on the junction surface between the silicon wafers is suppressed. Due to a recess made in the surface of a buried conductive film, a cavity is formed in the junction surface between the silicon wafers. The ends of the cavity extend to the periphery of the junction surface between the silicon wafers. This allows the air trapped on the junction surface between the silicon wafers to get out through the cavity, thereby reducing the possibility of generation of voids on the junction surface.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: April 2, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Mayu Aoki, Kenichi Takeda, Kazuyuki Hozawa
  • Publication number: 20120315710
    Abstract: In order to provide a method for producing semiconductor devices that can use the highly productive W to W method, and achieve a high yield, a method for producing semiconductor devices comprises a step (S401) in which a reconstituted wafer is prepared by replacing defective chips with non-defective chips, a step (S403) in which the reconstituted wafer and the base wafer are connected to one another by laminating, a step (S406) in which through-electrodes are formed in the reconstituted wafer, and a step (S409) in which a separate reconstituted wafer is laminated onto and connected to the reconstituted wafer having through-electrodes.
    Type: Application
    Filed: February 1, 2011
    Publication date: December 13, 2012
    Inventors: Kazuyuki Hozawa, Kenichi Takeda, Mayu Aoki
  • Publication number: 20120256311
    Abstract: A bump electrode, a dummy bump, and a heat-resistant polymer film, whose upper-surface heights are uniformed, are formed on each of a first silicon substrate and a second silicon substrate, and then, the first silicon substrate and the second silicon substrate are bonded to each other so that the bump electrodes formed on the respective substrates are electrically connected to each other. At this time, the dummy bump is arranged so as to be bonded to the heat-resistant polymer film on the silicon substrate opposed thereto, so that a semiconductor device having both of good electrical connection between the bump electrodes and bump protection performance obtained by a polymer film with high heat resistance and without voids can be achieved.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 11, 2012
    Inventors: Kenichi TAKEDA, Mayu AOKI, Kazuyuki HOZAWA
  • Publication number: 20120098106
    Abstract: When a silicon through electrode is to be formed from a back surface (the surface on which a semiconductor device is not formed) of a silicon substrate, a wide range of an interlayer insulating film made of a Low-k material absorbs moisture, and there is a problem that the electrical characteristics of wiring are degraded. The above-described problem can be solved by forming at least a single ring-shaped frame laid out to enclose the silicon through electrode by using metal wirings in plural layers and a connection via connecting the upper and lower metal wirings in a Low-k material layer penetrated by the silicon through electrode and by forming a moisture barrier film made up of at least a metal wiring and a connection via between the silicon through electrode and a circuit wiring formed in the vicinity of the silicon through electrode.
    Type: Application
    Filed: July 1, 2009
    Publication date: April 26, 2012
    Inventors: Mayu Aoki, Kenichi Takeda, Kazuyuki Hozawa
  • Publication number: 20120068355
    Abstract: A semiconductor device including two silicon wafers stacked and bonded together with bumps of one wafer electrically coupled with those of the other wafer, in which generation of voids on the junction surface between the silicon wafers is suppressed. Due to a recess made in the surface of a buried conductive film, a cavity is formed in the junction surface between the silicon wafers. The ends of the cavity extend to the periphery of the junction surface between the silicon wafers. This allows the air trapped on the junction surface between the silicon wafers to get out through the cavity, thereby reducing the possibility of generation of voids on the junction surface.
    Type: Application
    Filed: July 7, 2011
    Publication date: March 22, 2012
    Inventors: Mayu Aoki, Kenichi Takeda, Kazuyuki Hozawa
  • Publication number: 20090230530
    Abstract: A back side of the silicon semiconductor substrate is roughly ground and is finishing-ground by using a whetstone having a copper content of less than 1 ppm, the back side being an opposite side of a side on which the semiconductor element is formed. The back side of the silicon semiconductor substrate is cleaned by the silicon chemical etching. A part up to depth of 3 nm from the back side of the silicon semiconductor substrate comprises copper of 1×109/cm2 or less.
    Type: Application
    Filed: November 6, 2008
    Publication date: September 17, 2009
    Applicant: Elpida Memory, Inc.
    Inventors: Kiyonori OYU, Kazuyuki Hozawa
  • Publication number: 20080076232
    Abstract: A method of removing impurities on a grinding surface of a thinned semiconductor wafer for producing a highly reliable semiconductor device is provided even when the thickness of a semiconductor chip is thinned. After grinding the back surface of the semiconductor wafer, the impurities on the grinding surface are removed by sandblast processing. The sand particles used in the sandblast processing do not contain copper or nickel, and a concentration of copper or nickel contained in the particles is desirably 1014 atoms·cm?3 or less. After the sandblast processing, compress air is jetted onto the grinding surface of the thinned semiconductor wafer, thereby removing foreign substances, surplus particles or the like on the grinding surface. Then, semiconductor chips are obtained by dicing the thinned semiconductor wafer.
    Type: Application
    Filed: July 18, 2007
    Publication date: March 27, 2008
    Inventor: Kazuyuki HOZAWA
  • Patent number: 7300833
    Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: November 27, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Naoki Yamamoto, Hiroyuki Uchiyama, Norio Suzuki, Eisuke Nishitani, Shin'ichiro Kimura, Kazuyuki Hozawa
  • Publication number: 20070048917
    Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.
    Type: Application
    Filed: October 27, 2006
    Publication date: March 1, 2007
    Inventors: Naoki Yamamoto, Hiroyuki Uchiyama, Norio Suzuki, Eisuke Nishitani, Shin'ichiro Kimura, Kazuyuki Hozawa
  • Patent number: 7144766
    Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: December 5, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Naoki Yamamoto, Hiroyuki Uchiyama, Norio Suzuki, Eisuke Nishitani, Shin'ichiro Kimura, Kazuyuki Hozawa