Abstract: An internal connection output pad (14A) connected to a CMOS output circuit (15A, 16A) on a first chip (11A) is electrically connected via a chip-to-chip bonding wire (17) to an internal connection input pad (14B) connected to a CMOS input circuit (15B, 16B) on a second chip (11B). In order to inspect the presence or absence of leakage resistance (40), a test circuit (30) controls a high-impedance output state, a high-level output state and a low-level output state of the internal connection output pad (14A) via the CMOS output circuit (15A, 16A). If a difference between a value obtained by measuring a current flowing through a power supply to a ground in the high-impedance output state and a value obtained by measuring such a current in the high-level output state is calculated, a transistor leakage current is canceled, so that a correct minute leakage current can be detected.

Abstract: An internal connection output pad (14A) connected to a CMOS output circuit (15A, 16A) on a first chip (11A) is electrically connected via a chip-to-chip bonding wire (17) to an internal connection input pad (14B) connected to a CMOS input circuit (15B, 16B) on a second chip (11B). In order to inspect the presence or absence of leakage resistance (40), a test circuit (30) controls a high-impedance output state, a high-level output state and a low-level output state of the internal connection output pad (14A) via the CMOS output circuit (15A, 16A). If a difference between a value obtained by measuring a current flowing through a power supply to a ground in the high-impedance output state and a value obtained by measuring such a current in the high-level output state is calculated, a transistor leakage current is canceled, so that a correct minute leakage current can be detected.

Abstract: To provide a D/A conversion apparatus that can minimize the increase in the amount of circuitry if the number of output levels is increased, a digital input value, input for each sampling clock, is first converted by a digital filter and a noise shaper into a word length limited digital signal with a high sampling frequency. The output of the noise shaper is mapped by a decoder to n m-valued signals a “1” at a time in a cyclic fashion progressing from one signal to the next so that the sum of the n m-valued signals becomes equal to the digital input value; thereafter, the n m-valued signals are converted by n m-valued D/A converters into corresponding analog signals which are then summed together by an analog adder to produce an analog output signal.