Abstract: A photo-alignment thermosetting liquid crystal composition including: a side-chain liquid crystal polymer which contains a liquid crystal constitutional unit containing a liquid crystal moiety in a side chain and a non-liquid crystal constitutional unit containing an alkylene group in a side chain, a copolymer which contains a photo-alignment constitutional unit containing a photo-alignment group in a side chain and a thermally crosslinkable constitutional unit containing a thermally crosslinkable group in a side chain, and in which the photo-alignment constitutional unit does not contain a linear alkylene group between the photo-alignment group and a monomer unit, and a thermal crosslinking agent for bonding to the thermally crosslinkable group of the thermally crosslinkable constitutional unit.

Abstract: A layout method of a semiconductor integrated circuit according to the present invention includes selecting M (M is an integer of two or larger and N or smaller) pieces of sequential circuits from N (N is an integer of three or larger) pieces of sequential circuits mounted on the semiconductor integrated circuit, a clock being distributed to the N pieces of sequential circuits from the same clock route; and replacing the M pieces of sequential circuits that are selected with one multi-data input/output sequential circuit including M pieces of input terminals and output terminals and one clock terminal that receives the clock distributed from the clock route.

Abstract: A method that achieves convergence of a hold time error in a relatively easy way without causing a setup time error even when the hold time error occurs in a large circuit, a device and a computer-readable storage medium storing a program therefor are provided. Group a first error path and a second error path in error paths which a hold time error occurs if there is a sharing path that shares its start point with the first error path and also shares its end point with the second error path, and insert a delay element without causing a setup time error per the grouped error paths. Convergence of a hold time error can be achieved without taking into account of a node that is not included in the group and there is no worry about causing a setup time error in a path that is not included in the group.

Abstract: A timing analysis method includes performing voltage drop analysis of a circuit laid out on a semiconductor chip, creating a voltage drop region file representing voltage drop on the semiconductor chip as regions at given voltage ranges based on a result of the voltage drop analysis, calculating second OCV factors respectively corresponding to the given voltage ranges contained in the voltage drop region file for each of the regions by using an OCV factor file containing first OCV factors representing variation of delay in association with given voltages in consideration of voltage drop, creating an OCV region file containing the calculated second OCV factors and the regions in association with each other, performing delay calculation of the laid-out circuit by using a delay library, and performing timing analysis by using the delay calculation result and the second OCV factors for each of the regions contained in the OCV region file.

Abstract: Provided is a clock gating circuit which receives a first clock signal and controls an output of a second clock signal corresponding to the first clock signal in response to a control signal. The clock gating circuit includes: a first latch that latches a signal value of the control signal in synchronization with the first clock signal; an AND that receives the first clock signal and controls an output of the second clock signal in response to an output signal of the first latch; and a second latch that latches a signal value of the output signal of the first latch in synchronization with the first clock signal, and outputs a latched value. This enables execution of a scan test with a simple circuit configuration.

Abstract: A layout method of a semiconductor integrated circuit according to the present invention includes selecting M (M is an integer of two or larger and N or smaller) pieces of sequential circuits from N (N is an integer of three or larger) pieces of sequential circuits mounted on the semiconductor integrated circuit, a clock being distributed to the N pieces of sequential circuits from the same clock route; and replacing the M pieces of sequential circuits that are selected with one multi-data input/output sequential circuit including M pieces of input terminals and output terminals and one clock terminal that receives the clock distributed from the clock route.

Abstract: An integrated circuit is provided with a scan chain including a scan flip-flop and a dummy block. The dummy block has a clock terminal receiving a clock signal, a scan input terminal connected to a scan data line within the scan chain, and a scan output terminal connected to another scan data line within the scan chain. The dummy block is configured to output data on the scan output terminal in response to input data fed to the scan input terminal, not responsively to the clock signal.

Abstract: A method that achieves convergence of a hold time error in a relatively easy way without causing a setup time error even when the hold time error occurs in a large circuit, a device and a computer-readable storage medium storing a program therefor are provided. Group a first error path and a second error path in error paths which a hold time error occurs if there is a sharing path that shares its start point with the first error path and also shares its end point with the second error path, and insert a delay element without causing a setup time error per the grouped error paths. Convergence of a hold time error can be achieved without taking into account of a node that is not included in the group and there is no worry about causing a setup time error in a path that is not included in the group.

Abstract: Provided is a clock gating circuit which receives a first clock signal and controls an output of a second clock signal corresponding to the first clock signal in response to a control signal. The clock gating circuit includes: a first latch that latches a signal value of the control signal in synchronization with the first clock signal; an AND that receives the first clock signal and controls an output of the second clock signal in response to an output signal of the first latch; and a second latch that latches a signal value of the output signal of the first latch in synchronization with the first clock signal, and outputs a latched value. This enables execution of a scan test with a simple circuit configuration.

Abstract: An integrated circuit is provided with a scan chain including a scan flip-flop and a dummy block. The dummy block has a clock terminal receiving a clock signal, a scan input terminal connected to a scan data line within the scan chain, and a scan output terminal connected to another scan data line within the scan chain. The dummy block is configured to output data on the scan output terminal in response to input data fed to the scan input terminal, not responsively to the clock signal.

Abstract: A timing-driven layout method is provided, which realizes timing error convergence toward zero without any timing constraint file. (a) An initial layout result is generated through placement of functional blocks of the circuit and routing of wiring lines therefor. (b) Wiring capacitance values of the respective blocks are calculated using the initial layout result. (c) Fan-out capacitance limitation values of the respective blocks are calculated using the wiring capacitance values of the blocks. Each of the fan-out capacitance limitation values represents a maximum fan-out capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value. (d) A driving capability of each of the blocks is compared with its fan-out capacitance limitation value, thereby generating a comparison result.

Abstract: A timing-driven layout method is provided, which realizes timing error convergence toward zero without any timing constraint file. (a) An initial layout result is generated through placement of functional blocks of the circuit and routing of wiring lines therefor. (b) Wiring capacitance values of the respective blocks are calculated using the initial layout result. (c) Fan-out capacitance limitation values of the respective blocks are calculated using the wiring capacitance values of the blocks. Each of the fan-out capacitance limitation values represents a maximum fan-out capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value. (d) A driving capability of each of the blocks is compared with its fan-out capacitance limitation value, thereby generating a comparison result.

Abstract: A timing-driven layout method is provided, which realizes timing error convergence toward zero without any timing constraint file. (a) An initial layout result is generated through placement of functional blocks of the circuit and routing of wiring lines therefor. (b) Wiring capacitance values of the respective blocks are calculated using the initial layout result. (c) Fan-out capacitance limitation values of the respective blocks are calculated using the wiring capacitance values of the blocks. Each of the fan-out capacitance limitation values represents a maximum fan-out capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value. (d) A driving capability of each of the blocks is compared with its fan-out capacitance limitation value, thereby generating a comparison result.

Abstract: A timing-driven layout method is provided, which realizes timing error convergence toward zero without any timing constraint file. (a) An initial layout result is generated through placement of functional blocks of the circuit and routing of wiring lines therefor. (b) Wiring capacitance values of the respective blocks are calculated using the initial layout result. (c) Fan-out capacitance limitation values of the respective blocks are calculated using the wiring capacitance values of the blocks. Each of the fan-out capacitance limitation values represents a maximum fan-out capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value. (d) A driving capability of each of the blocks is compared with its fan-out capacitance limitation valuer thereby generating a comparison result.