Abstract: A reset control apparatus, which carries out reset control in response to an external reset signal, includes a count start signal generating unit for producing a count start signal in response to the external reset signal, a counter for starting counting in response to the count start signal, and a reset signal generating unit for outputting an internal reset signal in response to the external reset signal, and for halting the output of the internal reset signal while the counter counts a predetermined count value. The reset control apparatus can solve a problem of a conventional reset control apparatus in that when the pulse width of the external reset signal passing through a noise canceler is narrower than the period of the clock signal, it cannot sample the signal, and hence cannot generate the internal reset signal.

Abstract: A reset control apparatus, which carries out reset control in response to an external reset signal, includes a count start signal generating unit for producing a count start signal in response to the external reset signal, a counter for starting counting in response to the count start signal, and a reset signal generating unit for outputting an internal reset signal in response to the external reset signal, and for halting the output of the internal reset signal while the counter counts a predetermined count value. The reset control apparatus can solve a problem of a conventional reset control apparatus in that when the pulse width of the external reset signal passing through a noise canceler is narrower than the period of the clock signal, it cannot sample the signal, and hence cannot generate the internal reset signal.

Abstract: Analog input selection circuits comprising an input terminal, an output terminal, a transmission path extending between the input terminal and the output terminal, transmission switches that open or close the transmission path, an over-voltage protection switch which connects or does not connect the transmission path to the ground, a PMOS transistor provided between the input terminal and a power supply, and an NMOS transistor provided between the input terminal and the ground are formed on an identical semiconductor substrate. If the semiconductor substrate is P-type, then a region in which the NMOS transistor is formed is surrounded by an N-well region.

Abstract: A timer control circuit includes timers that perform count operations. A signal selection circuit selectively passes underflow signals supplied from the timers, based on control signals. A flip-flop is supplied with an output of the signal selection circuit section as a toggle signal.

Abstract: The timer control circuit includes plurality of timers that perform predetermined count operations. The signal selection circuit section allows to selectively pass underflow signals supplied from the timers based on the control signals. The flip-flop is supplied with an output of the signal selection circuit section a toggle signal.

Abstract: It is an object to realize in a floating point computation device a normalization circuit device which carries out normalization, unnormalization and 0 function operation at high speed. A circuit (3) outputs 1 from the most significant bit for the number obtained by adding 1 to a decimal number value of the exponent part input signal (A). AND operation of the signal (A") and the mantissa part input signal (B) and OR operation of all bits of the value ((3) provide a control signal (G'). A circuit (2) represents in a binary value (B') a number obtained by subtracting 1 from a number value of the bit position of the leading 1 from the most significant bit of the signal (B). A circuit (6) subtracts the valve (B') from the signal (A) and a circuit (7b) selects the signal (H) and a 0 value according to the signal (G') to obtain an exponent part output signal (C) after normalization.