Patents by Inventor Kazuyuki Kaino
Kazuyuki Kaino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7279357Abstract: A semiconductor device has a semiconductor chip, a first insulating film and an inductor. The semiconductor chip includes an integrated circuit formed on the main surface of the chip and a plurality of pad electrodes formed on the main surface of the chip and electrically connected to the integrated circuit. The first insulating film of an insulating resin material is formed on the main surface of the semiconductor chip, covers the integrated circuit, and includes a plurality of contact holes provided on the respective pad electrodes. The inductor is formed on the inductor formation region of the first insulating film, and both terminals of the inductor are connected to the pad electrodes through the contact holes, respectively. The inductor formation region of the first insulating film is formed thicker than a portion of the first insulating film around the contact hole.Type: GrantFiled: May 5, 2005Date of Patent: October 9, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Nozomi Shimoishizaka, Kazuyuki Kaino, Yoshifumi Nakamura, Keiji Miki, Kazumi Watase, Ryuichi Sahara
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Publication number: 20050199979Abstract: A semiconductor device has a semiconductor chip, a first insulating film and an inductor. The semiconductor chip includes an integrated circuit formed on the main surface of the chip and a plurality of pad electrodes formed on the main surface of the chip and electrically connected to the integrated circuit. The first insulating film of an insulating resin material is formed on the main surface of the semiconductor chip, covers the integrated circuit, and includes a plurality of contact holes provided on the respective pad electrodes. The inductor is formed on the inductor formation region of the first insulating film, and both terminals of the inductor are connected to the pad electrodes through the contact holes, respectively. The inductor formation region of the first insulating film is formed thicker than a portion of the first insulating film around the contact hole.Type: ApplicationFiled: May 5, 2005Publication date: September 15, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Nozomi Shimoishizaka, Kazuyuki Kaino, Yoshifumi Nakamura, Keiji Miki, Kazumi Watase, Ryuichi Sahara
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Patent number: 6924173Abstract: Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.Type: GrantFiled: March 14, 2003Date of Patent: August 2, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazumi Watase, Hiroaki Fujimoto, Ryuichi Sahara, Nozomi Shimoishizaka, Takahiro Kumakawa, Kazuyuki Kaino, Yoshifumi Nakamura
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Patent number: 6914331Abstract: A semiconductor device has a semiconductor chip, a first insulating film and an inductor. The semiconductor chip includes an integrated circuit formed on the main surface of the chip and a plurality of pad electrodes formed on the main surface of the chip and electrically connected to the integrated circuit. The first insulating film of an insulating resin material is formed on the main surface of the semiconductor chip, covers the integrated circuit, and includes a plurality of contact holes provided on the respective pad electrodes. The inductor is formed on the inductor formation region of the first insulating film, and both terminals of the inductor are connected to the pad electrodes through the contact holes, respectively. The inductor formation region of the first insulating film is formed thicker than a portion of the first insulating film around the contact hole.Type: GrantFiled: May 21, 2003Date of Patent: July 5, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Nozomi Shimoishizaka, Kazuyuki Kaino, Yoshifumi Nakamura, Keiji Miki, Kazumi Watase, Ryuichi Sahara
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Publication number: 20030218247Abstract: A semiconductor device has a semiconductor chip, a first insulating film and an inductor. The semiconductor chip includes an integrated circuit formed on the main surface of the chip and a plurality of pad electrodes formed on the main surface of the chip and electrically connected to the integrated circuit. The first insulating film of an insulating resin material is formed on the main surface of the semiconductor chip, covers the integrated circuit, and includes a plurality of contact holes provided on the respective pad electrodes. The inductor is formed on the inductor formation region of the first insulating film, and both terminals of the inductor are connected to the pad electrodes through the contact holes, respectively. The inductor formation region of the first insulating film is formed thicker than a portion of the first insulating film around the contact hole.Type: ApplicationFiled: May 21, 2003Publication date: November 27, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Nozomi Shimoishizaka, Kazuyuki Kaino, Yoshifumi Nakamura, Keiji Miki, Kazumi Watase, Ryuichi Sahara
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Publication number: 20030194834Abstract: Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.Type: ApplicationFiled: March 14, 2003Publication date: October 16, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kazumi Watase, Hiroaki Fujimoto, Ryuichi Sahara, Nozomi Shimoishizaka, Takahiro Kumakawa, Kazuyuki Kaino, Yoshifumi Nakamura
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Patent number: 6559528Abstract: Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.Type: GrantFiled: February 20, 2001Date of Patent: May 6, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazumi Watase, Hiroaki Fujimoto, Ryuichi Sahara, Nozomi Shimoishizaka, Takahiro Kumakawa, Kazuyuki Kaino, Yoshifumi Nakamura
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Publication number: 20010015496Abstract: Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.Type: ApplicationFiled: February 20, 2001Publication date: August 23, 2001Inventors: Kazumi Watase, Hiroaki Fujimoto, Ryuichi Sahara, Nozomi Shimoishizaka, Takahiro Kumakawa, Kazuyuki Kaino, Yoshifumi Nakamura
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Patent number: 5650870Abstract: A rotary polygon mirror has reflecting mirror faces formed at side faces of a prism of a predetermined height, and includes an axially symmetrical projection formed along at least parts of outer peripheral edges of the prism on upper and lower faces of the prism.Type: GrantFiled: April 23, 1996Date of Patent: July 22, 1997Assignee: Matsushita Electronic Industrial Co., Ltd.Inventors: Kazuyuki Kaino, Yosuke Ogue
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Patent number: 5561545Abstract: A rotary polygon mirror has reflecting mirror faces formed at side faces of a prism of a predetermined height, and includes an axially symmetrical projection formed along at least parts of outer peripheral edges of the prism on upper and lower faces of the prism.Type: GrantFiled: June 14, 1994Date of Patent: October 1, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazuyuki Kaino, Yosuke Ogue
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Patent number: 5500069Abstract: A three-dimensional object-forming method for forming an object of a three-dimensional shape with photosetting resin, includes the following steps. The desired three-dimensional shape is represented by a set of data related to sectional shapes of the three-dimensional shape cut at predetermined intervals distance of. The laser light is scanned, from above a tank containing liquid of photosetting resin not yet hardened, outward around a predetermined point of each sectional shape in a manner to trace similar figures to an arbitrary shape, to thereby to set a surface of a resin layer in a shape corresponding to one sectional shape. The set resin layer is sunk into the liquid of the photosetting resin not yet hardened by a distance of a cross section. A plurality of the set resin layers of the photosetting resin is laminated by repeating the scanning and sinking steps on the basis of the set of data.Type: GrantFiled: April 14, 1994Date of Patent: March 19, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yousuke Ogue, Takahiro Kuyama, Kazuyuki Kaino
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Patent number: 5131559Abstract: A resin casing of a box-like configuration has side walls, a bottom wall and a plurality of partition walls. Each partition wall has two opposite end portions tapered, at which the partition wall is integrally formed with the side wall. Thus, the cooling speed is made constant at every portion in the resin casing to avoid shrinkage marks and unwanted raised lines.Type: GrantFiled: February 19, 1991Date of Patent: July 21, 1992Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hideho Ariyoshi, Kazuyuki Kaino