Patents by Inventor Kazuyuki Kamegaki
Kazuyuki Kamegaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7598605Abstract: A primary side circuit and a secondary side circuit are provided on first and second semiconductor substrates, respectively. A first capacitive insulator on the first substrate electrically insulates and isolates between the primary and secondary side circuits while permitting signal transmission between these circuits. A second capacitive insulator on the second semiconductor substrate electrically isolates the primary and secondary side circuit while permitting signal transmission therebetween. First and second frames are provided for input and output of signals to and from the primary and secondary side circuits. External electrodes of the first and second capacitive insulators are connected together by a third lead frame via a conductive adhesive body including more than one solder ball. The first and second substrates and the lead frames are sealed by a dielectric resin.Type: GrantFiled: July 31, 2006Date of Patent: October 6, 2009Assignee: Hitachi, Ltd.Inventors: Noboru Akiyama, Minehiro Nemoto, Seigou Yukutake, Yasuyuki Kojima, Kazuyuki Kamegaki
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Publication number: 20060267193Abstract: A primary side circuit and a secondary side circuit are provided on first and second semiconductor substrates, respectively. A first capacitive insulator on the first substrate electrically insulates and isolates between the primary and secondary side circuits while permitting signal transmission between these circuits. A second capacitive insulator on the second semiconductor substrate electrically isolates the primary and secondary side circuit while permitting signal transmission therebetween. First and second frames are provided for input and output of signals to and from the primary and secondary side circuits. External electrodes of the first and second capacitive insulators are connected together by a third lead frame via a conductive adhesive body including more than one solder ball. The first and second substrates and the lead frames are sealed by a dielectric resin.Type: ApplicationFiled: July 31, 2006Publication date: November 30, 2006Inventors: Noboru Akiyama, Minehiro Nemoto, Seigou Yukutake, Yasuyuki Kojima, Kazuyuki Kamegaki
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Patent number: 7091588Abstract: A primary side circuit and a secondary side circuit are provided on first and second semiconductor substrates, respectively. A first capacitive insulator on the first substrate electrically insulates and isolates between the primary and secondary side circuits while permitting signal transmission between these circuits. A second capacitive insulator on the second semiconductor substrate electrically isolates the primary and secondary side circuit while permitting signal transmission therebetween. First and second frames are provided for input and output of signals to and from the primary and secondary side circuits. External electrodes of the first and second capacitive insulators are connected together by a third lead frame via a conductive adhesive body including more than one solder ball. The first and second substrates and the lead frames are sealed by a dielectric resin.Type: GrantFiled: December 30, 2004Date of Patent: August 15, 2006Assignee: Hitachi, Ltd.Inventors: Noboru Akiyama, Minehiro Nemoto, Seigou Yukutake, Yasuyuki Kojima, Kazuyuki Kamegaki
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Publication number: 20050112932Abstract: A primary side circuit and a secondary side circuit are provided on first and second semiconductor substrates, respectively. A first capacitive insulator on the first substrate electrically insulates and isolates between the primary and secondary side circuits while permitting signal transmission between these circuits. A second capacitive insulator on the second semiconductor substrate electrically isolates the primary and secondary side circuit while permitting signal transmission therebetween. First and second frames are provided for input and output of signals to and from the primary and secondary side circuits. External electrodes of the first and second capacitive insulators are connected together by a third lead frame via a conductive adhesive body including more than one solder ball. The first and second substrates and the lead frames are sealed by a dielectric resin.Type: ApplicationFiled: December 30, 2004Publication date: May 26, 2005Inventors: Noboru Akiyama, Minehiro Nemoto, Seigou Yukutake, Yasuyuki Kojima, Kazuyuki Kamegaki
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Patent number: 6853063Abstract: Wire bonding or printed wiring board leads or, alternatively, lead frames or equivalents thereof are used to electrically connect external electrodes of high withstand voltage capacitors formed on a plurality of semiconductor chips. A driver circuit for signal transmission or receiver circuit for signal receipt formed on the semiconductor chips are electrically connected with substrate-side electrodes of said high withstand voltage capacitors, causing the plurality of semiconductor chips to be received within either a single package or a single module. Using this arrangement, a semiconductor device is capable of achieving both dielectricity and size reduction.Type: GrantFiled: May 22, 2003Date of Patent: February 8, 2005Assignee: Hitachi, Ltd.Inventors: Noboru Akiyama, Minehiro Nemoto, Seigou Yukutake, Yasuyuki Kojima, Kazuyuki Kamegaki
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Publication number: 20030201523Abstract: Wire bonding or printed wiring board leads or, alternatively, lead frames or equivalents thereof are used to electrically connect external electrodes of high withstand voltage capacitors formed on a plurality of semiconductor chips. A driver circuit for signal transmission or receiver circuit for signal receipt formed on the semiconductor chips are electrically connected with substrate-side electrodes of said high withstand voltage capacitors, causing the plurality of semiconductor chips to be received within either a single package or a single module. Using this arrangement, a semiconductor device is capable of achieving both dielectricity and size reduction.Type: ApplicationFiled: May 22, 2003Publication date: October 30, 2003Inventors: Noboru Akiyama, Minehiro Nemoto, Seigou Yukutake, Yasuyuki Kojima, Kazuyuki Kamegaki
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Patent number: 6611051Abstract: Wire bonding or printed wiring board leads or, alternatively, lead frames or equivalents thereof are used to electrically connect external electrodes of high withstand voltage capacitors formed on a plurality of semiconductor chips. A driver circuit for signal transmission or receiver circuit for signal receipt formed on the semiconductor chips are electrically connected with substrate-side electrodes of said high withstand voltage capacitors, causing the plurality of semiconductor chips to be received within either a single package or a single module. Using this arrangement, a semiconductor device is capable of achieving both dielectricity and size reduction.Type: GrantFiled: September 28, 2001Date of Patent: August 26, 2003Assignee: Hitachi, Ltd.Inventors: Noboru Akiyama, Minehiro Nemoto, Seigou Yukutake, Yasuyuki Kojima, Kazuyuki Kamegaki
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Publication number: 20020125555Abstract: Wire bonding or printed wiring board leads or alternatively lead frames or equivalents thereof are used to electrically connect among external electrodes of high withstand voltage capacitors as formed on a plurality of semiconductor chips. A driver circuitry for signal transmission or receiver circuitry for signal receipt being formed on the semiconductor chips is electrically connected with substrate-side electrodes of said high withstand voltage capacitors, causing said plurality of semiconductor chips to be received within either a single package or a single module. Whereby a semiconductor device is capable of achieving both dielectricity and size reduction.Type: ApplicationFiled: September 28, 2001Publication date: September 12, 2002Inventors: Noboru Akiyama, Minehiro Nemoto, Seigou Yukutake, Yasuyuki Kojima, Kazuyuki Kamegaki
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Patent number: 5300798Abstract: When a semiconductor integrated circuit device having a wiring structure of three or more layers is hierarchically considered as a collection of a plurality of functional blocks, each functional block is internally connected by wirings in the first wiring layer, in which wirings have their main extended direction prescribed to be the X-direction, and wirings in the second wiring layer, in which wirings have their main extended direction prescribed to be the Y-direction, formed over the first wiring layer. Wirings in the third wiring layer, in which wirings have their main extended direction prescribed to be the same as the wirings in the second wiring layer, formed over the second wiring layer, together with wirings in the first and second wiring layer, are used as signal wirings between functional blocks, while the wirings in the third wiring layer are used as power supply wirings for providing power supply to functional blocks.Type: GrantFiled: November 17, 1992Date of Patent: April 5, 1994Assignees: Hitachi, Ltd., Hitachi Microcomputer System, Ltd., Hitachi Tobu Semiconductor, Ltd., Hitachi Communication Systems, IncorporatedInventors: Kouichi Yamazaki, Setsuo Ogura, Kazuyuki Kamegaki, Kenya Yamauchi, Yukinori Kitamura, Tuyoshi Nagase
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Patent number: 5132806Abstract: Disclosed is a novel semiconductor integrated circuit device for use in a color VTR (Video Tape Recorder). Concretely, the semiconductor integrated circuit device comprises a substantially rectangular semiconductor chip which has a principal surface, a luminance signal processing unit and a color signal processing unit which are disposed at the positions of the principal surface opposing to each other, and a semiconductor region which is provided in the interspace of the principal surface between the luminance signal and color signal processing units opposing to each other and which is supplied with a bias stable A.C.-wise. Further, the semiconductor region is located substantially at the central portion of the semiconductor chip and is extended so as to intersect with one set of opposing sides of the rectangular semiconductor chip.Type: GrantFiled: June 15, 1990Date of Patent: July 21, 1992Assignees: Hitachi, Ltd., Hitachi MicrocomputerInventors: Yukinori Kitamura, Setsuo Ogura, Shiro Mayuzumi, Shunji Mori, Toshiyuki Fukamachi, Yuji Kobayashi, Kouichi Yamazaki, Makoto Furihata, Kazuyuki Kamegaki
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Patent number: 4857987Abstract: Herein disclosed is a semiconductor device including a plurality of IIL elements which are electrically connected by a plurality of first wirings arranged generally parallel with one another and a plurality of second wirings arranged generally parallel with one another and extended in different direction to the first wirings.Type: GrantFiled: September 19, 1988Date of Patent: August 15, 1989Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.Inventors: Setsuo Ogura, Kazuyuki Kamegaki, Kouichi Yamazaki, Hideo Miyazaki, Yukinori Kitamura, Shirou Mayuzumi
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Patent number: 4789884Abstract: A multi-stage IIL circuit is provided which includes common IIL elements each using a PNP transistor as an injector and an NPN transistor as an inverter, and inverse IIL elements each using an NPN transistor as an injector and a PNP transistor as an inverter.Type: GrantFiled: April 14, 1986Date of Patent: December 6, 1988Assignee: Hitachi, Ltd.Inventors: Shigeaki Minamihata, Kazuyuki Kamegaki