Abstract: Timing verification method includes processes wherein timing analysis is performed taking voltage drop of a laid out circuit into consideration and a changing instruction list for changing the laid out circuit is produced based on a result of the timing analysis. Then, in a first-time timing verification process, voltage drop analysis is performed for the laid out circuit so that a voltage drop list is produced based on a result of the voltage drop analysis and timing analysis is performed using the voltage drop list, and, in a later timing verification process, the voltage drop list is updated based on the changing instruction list and the timing analysis is performed using the updated voltage drop list.

Abstract: Timing verification method includes processes wherein timing analysis is performed taking voltage drop of a laid out circuit into consideration and a changing instruction list for changing the laid out circuit is produced based on a result of the timing analysis. Then, in a first-time timing verification process, voltage drop analysis is performed for the laid out circuit so that a voltage drop list is produced based on a result of the voltage drop analysis and timing analysis is performed using the voltage drop list, and, in a later timing verification process, the voltage drop list is updated based on the changing instruction list and the timing analysis is performed using the updated voltage drop list.

Abstract: An arranging unit arranges a cell obtained from a net list input by an input unit on a large scale integration chip. A net extracting unit extracts an arbitrary net to be tested from a set of the cells arranged. An information extracting unit extracts, based on correlation information between information on a driving capacity of each of cells included in a circuit created based on a delay time caused by a crosstalk occurred as a result of a circuit simulation for a predetermined circuit model and information on a length of a wiring that connects the cells, wire-length information that has a correlation with information on the driving capacity of the cell in the net. An inserting unit inserts, based on the wire-length information, a delay-time suppressing cell to suppress a delay time in the net.

Abstract: An arranging unit arranges a cell obtained from a net list input by an input unit on a large scale integration chip. A net extracting unit extracts an arbitrary net to be tested from a set of the cells arranged. An information extracting unit extracts, based on correlation information between information on a driving capacity of each of cells included in a circuit created based on a delay time caused by a crosstalk occurred as a result of a circuit simulation for a predetermined circuit model and information on a length of a wiring that connects the cells, wire-length information that has a correlation with information on the driving capacity of the cell in the net. An inserting unit inserts, based on the wire-length information, a delay-time suppressing cell to suppress a delay time in the net.

Abstract: Circuit blocks each of which is within a predetermined scale are formed based on a read-out net list. Each circuit block is subjected to a dynamic timing analysis, and a delay characteristic library including obtained analysis results is generated. A static timing analysis is performed based on the delay characteristic library. In this manner, the transmission delay of a desired signal path is analyzed in such a manner that the circuit to be analyzed that is indicated by the net list is regarded to be constructed by the above circuit blocks. A delay characteristic analyzing method is provided that can shorten the processing time while maintaining a high degree of freedom of LSI designing and high accuracy of critical path determination in transistor-level full custom LSI designing.

Abstract: Circuit blocks each of which is within a predetermined scale are formed based on a read-out net list. Each circuit block is subjected to a dynamic timing analysis, and a delay characteristic library including obtained analysis results is generated. A static timing analysis is performed based on the delay characteristic library. In this manner, the transmission delay of a desired signal path is analyzed in such a manner that the circuit to be analyzed that is indicated by the net list is regarded to be constructed by the above circuit blocks. A delay characteristic analyzing method is provided that can shorten the processing time while maintaining a high degree of freedom of LSI designing and high accuracy of critical path determination in transistor-level full custom LSI designing.

Abstract: A constant multiplier reduces the number of partial products and thereby reduces the number of adding stages for a constant. By reducing the number of partial products, the constant multiplier reduces circuit area and operation delay. The constant multiplier is optionally incorporated into a corresponding method and a device which automatically provides the constant multiplier. The constant multiplier includes an adding/subtracting circuit, which has an adder and inverter, for performing addition and subtraction of partial products. Each of the partial products is obtained by multiplying each of “add” and “subtract” terms of a power of two having a smallest term number obtained by decomposing the constant by a signal. The constant multiplier is suitably used for designing a large scale integrated circuit (ASIC) having functions of a moving picture expert group (MPEG).