Abstract: A nonvolatile semiconductor memory device includes a memory cell array, a plurality of word lines, a plurality of digit lines, a data setting circuit, a write data latch circuit, an X decoder, a write circuit, and a timing control circuit. In the memory cell array, memory cells are arranged in a matrix. Each word line is commonly connected to the memory cells of a corresponding page. Each digit line is commonly connected to the memory cells of a corresponding bit and address. The data setting circuit inverts input data in an erase mode and directly outputs it in a write mode. The write data latch circuit latches data output from the data setting circuit in correspondence with a bit and address designated by an address signal. The X decoder selects a word line corresponding to a page designated by an address signal out of the word lines upon reception of a simultaneous write start signal.

Abstract: A semiconductor device includes a semiconductor chip, a protective wiring layer, and an abnormality detector. At least one of integrated circuits is formed on the semiconductor chip. The protective wiring layer is formed to be spread on the integrated circuit at a very small interval, and made of a conductive light-shielding material. The protective wiring layer is applied with a power supply voltage upon operating the integrated circuit. The abnormality detector monitors the voltage applied to the protective wiring layer and outputs an abnormality detection signal when the monitored voltage is an abnormal voltage.

Abstract: A decoding and level shifting circuit comprises first and second n-channel transistors each having a source connected to a high negative potential, a gate and a drain of the first n-channel transistor being connected to a drain and a gate of the second n-channel transistor, respectively. A first group of p-channel transistors are connected in parallel between the drain of the first n-channel transistor and a ground level, and gates of the first group of p-channel transistors are connected to receive a first group of signals, respectively. A second group of p-channel transistors are connected in series between the drain of the second n-channel transistor and the ground level, and gates of the second group of p-channel transistors are connected to respectively receive a second group of signals complementary to the first group of signals. The drain of the second n-channel transistor gives an output.