Abstract: In a MOSFET having a polysilicon gate electrode, the polysilicon layer of the gate electrode is nonuniformly doped with an impurity for the same type of conductivity as the source and drain regions such that the effective impurity concentration gradually and continuously decreases from a top section toward a bottom section adjacent to the gate oxide film and becomes minimum in the bottom section. When a high voltage is applied between the drain and the gate, a depletion layer is created in the bottom section of the polysilicon layer, whereby the electric field on the gate oxide film is reduced. Accordingly, the thickness of the gate oxide film can be reduced for high-speed operation. Besides, this MOSFET is useful in a high-voltage interface for a MOS circuit operated at a low supply voltage. The doping of the polysilicon layer is accomplished by ion implantation. It is suitable to employ a lightly doped drain (LDD) structure in this MOSFET.

Abstract: An underlying interconnecting layer is formed on a semiconductor substrate and a first insulating layer is formed on the underlying interconnecting layer and these are patterned. Next, a second insulating layer which is different in material from the first insulating layer is formed on the patterned first insulating layer and the semiconductor substrate and a portion of the second insulating layer is removed by etching to expose a portion of the first insulating layer. Next, the exposed first insulating layer is removed by etching. Next, a conductive layer is implanted in a through hole which is made in the removed first insulating layer and removed second insulating layer. Interconnecting layers are then formed on the conductive layer and the second insulating layer.

Abstract: An MOS semiconductor device containing an MOSFET with an asymmetric LDD structure, which has in a semiconductor substrate a first heavily doped region, a lightly doped region formed adjacent to the first heavily doped region, and a second heavily doped region formed apart from the first lightly doped region. The first heavily doped region and the lightly doped region act as a drain region of the MOSFET, and the second heavily doped region acts as a source region thereof. A gate electrode composed of a plurality of parts is positioned over a channel region. At least one of the parts has a drain-side end positioned over the lightly doped region and a source-side end positioned over the channel region not to extend to the second heavily doped region. Free design can be realized without layout restriction and fabricated with high reproducibility in large quantities.

Abstract: First plugs project from a lower inter-level insulating layer so as to be coplanar with an upper surface of a middle-level wiring on the lower-level insulating layer, and through-holes are formed in an upper inter-level insulating layer over the middle-level wiring and the first plug without an over-etching, thereby allowing second plugs in the through-holes to be directly held in contact with the middle-level wiring and the first plug.

Abstract: A method for manufacturing a semiconductor device of the present invention comprises the following steps (1) through (7) of, (1) forming a lower insulation film thicker than a metal wiring layer to be formed in order on a semiconductor substrate, a first conductive film and an upper insulation film; (2) removing the upper insulation film in the wiring formation area and then exposing the lower insulation film by etching the first conductive film; (3) forming concave grooves in the lower insulation film by etching the film using as a mask the upper insulation film whose wiring formation area is removed or a photoresist applied to the patterning of the upper insulation film; (4) forming a second conductive film on the whole surface including the concave grooves and successively forming sidewalls made of the insulation film in the sides of the grooves; (5) forming metallic wiring layers by electrolytic plating in the grooves wherein the said sidewalls have been formed by electric power supplied from the second c

Abstract: A semiconductor device according to the present invention includes a lower conductive layer having a plurality of dummy conductive lines in addition to operative conductive lines. The operative and dummy conductive lines are connected to an electrode pad of upper conductive layer by through holes. The upper and lower conductive layers are insulated from each other by an interfacial insulation layer.

Abstract: In a multi-level wiring structure of an IC device, an intermediate insulating layer on a portion of a field insulating layer where wiring layers are absent thereabove is selectively removed so that a gas gap is formed between lower wiring layers.

Abstract: A semiconductor integrated circuit is constituted, by forming selectively a first insulation film on a lower layer wiring metal; after covering a lateral wall of the lower layer wiring metal with a second insulation film, embedding a material having a low dielectric constant in the lower layer wiring so as to flatten the surface thereof. A third insulation film is formed over the entire surface, and through holes are made in the first and the third insulation films on the lower layer wiring so as to connect the lower layer wiring to the upper layer wiring through the through holes. Thus, it is possible to realize a layer insulation film having very good flatness, to realize a multilayer wiring having high reliability in which corrosions, etc., are not caused in the wiring metal containing through hole portions, and to make the coated films thicker, which films have a low dielectric constant and can be relatively easily formed, so that the wiring capacity can be decreased.

Abstract: A wiring method for semiconductor device includes the steps of forming a first seat in a portion where a lower wiring layer and an upper wiring layer are to be connected on a semiconductor substrate provided with semiconductor elements, forming a first conductor composed of an Al or Al-Cu alloy on the whole surface of the semiconductor substrate; forming the lower wiring layer by selectively removing the first conductor simultaneously with the formation of a second seat composed of the first conductor on the first seat; forming by the coating method a glass or organic silicon compound film as an interlevel insulating film, forming a through-hole by photoetching in the portion where the upper and lower wiring layers are to be connected; and forming a second conductor in order to form the upper wiring layer by photoetching.

Abstract: A multi-level semiconductor structure forming a part of a semiconductor device has a narrow wiring strip and a wide wiring strip formed on a lower insulating film, an inter-level insulating film structure covering the narrow and wide wiring strips, an upper insulating film provided on the inter-level insulating film structure and upper metal wiring strips formed on the upper insulating film and contacting respective contact areas of the narrow and wide wiring strips through contact holes formed through the upper insulating film as well as the inter-level insulating film structure, respectively, and the inter-level insulating structure consists of a first film deposited on the entire surface and a second film filling a gap between adjacent lower wiring strips for creating a smooth topography; the second film tends to be left on the wide wiring strip after an etch-back stage and is causative of erosion of the metal wiring strip, so that a plurality of moats are formed in the wide wiring strip for surrounding th

Abstract: A multi-level semiconductor structure forming a part of a semiconductor device has a narrow wiring strip and a wide wiring strip formed on a lower insulating film, an inter-level insulating film structure covering the narrow and wide wiring strips, an upper insulating film provided on the inter-level insulating film structure and upper metal wiring strips formed on the upper insulating film and contacting respective contact areas of the narrow and wide wiring strips through contact holes formed through the upper insulating film as well as the inter-level insulating film structure, respectively, and the inter-level insulating structure consists of a first film deposited on the entire surface and a second film filling a gap between adjacent lower wiring strips for creating a smooth topography; the second film tends to be left on the wide wiring strip after an etch-back stage and is causative of erosion of the metal wiring strip, so that a plurality of moats are formed in the wide wiring strip for surrounding th