Patents by Inventor Kazuyuki Morishige
Kazuyuki Morishige has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11705188Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.Type: GrantFiled: November 17, 2021Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Toshiaki Tsukihashi, Kenichi Watanabe, Kazuyuki Morishige, Moeha Shibuya, Kumiko Ishii
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Publication number: 20230206966Abstract: Disclosed herein is an apparatus that includes a first wiring layer including first and second conductive patterns extending in a second direction and coupled to source and drain regions, respectively, and a second wiring layer including third and fourth conductive patterns extending in the second direction and coupled to the first and second conductive patterns, respectively. The first conductive pattern has first and second sections arranged in the second direction, and the second conductive pattern has third and fourth sections arranged in the second direction. The first and fourth sections are arranged in a first direction, and the second and third sections are arranged in the first direction. The third conductive pattern covers the first section without covering the second section. The fourth conductive pattern covers the third section without covering the fourth section.Type: ApplicationFiled: December 28, 2021Publication date: June 29, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Mieko Kojima, Kazuyuki Morishige, Tetsuya Arai, Guangcan Chen
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Publication number: 20220076736Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.Type: ApplicationFiled: November 17, 2021Publication date: March 10, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Toshiaki Tsukihashi, Kenichi Watanabe, Kazuyuki Morishige, Moeha Shibuya, Kumiko Ishii
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Patent number: 11183232Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.Type: GrantFiled: February 25, 2020Date of Patent: November 23, 2021Assignee: Micron Technology, Inc.Inventors: Toshiaki Tsukihashi, Kenichi Watanabe, Kazuyuki Morishige, Moeha Shibuya, Kumiko Ishii
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Publication number: 20210264967Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.Type: ApplicationFiled: February 25, 2020Publication date: August 26, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Toshiaki Tsukihashi, Kenichi Watanabe, Kazuyuki Morishige, Moeha Shibuya, Kumiko Ishii
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Patent number: 10896720Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for drivers with reduced voltage noise. Clock signals may be provided to semiconductor devices, and may be distributed throughout the device. Driven are provided along signal paths within the device which may act as buffers for the clock signals. Each clock signal may be coupled to multiple driver circuits within the driver. Each of the multiple driver circuits may be coupled to a different pair of power supply voltage lines. The driver circuits may all have a similar delay to each other.Type: GrantFiled: November 22, 2019Date of Patent: January 19, 2021Assignee: Micron Technology, Inc.Inventor: Kazuyuki Morishige
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Publication number: 20200105333Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for drivers with reduced voltage noise. Clock signals may be provided to semiconductor devices, and may be distributed throughout the device. Driven are provided along signal paths within the device which may act as buffers for the clock signals. Each clock signal may be coupled to multiple driver circuits within the driver. Each of the multiple driver circuits may be coupled to a different pair of power supply voltage lines. The driver circuits may all have a similar delay to each other.Type: ApplicationFiled: November 22, 2019Publication date: April 2, 2020Applicant: MICRON TECHNOLOGY, INC.Inventor: Kazuyuki Morishige
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Patent number: 10522208Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for drivers with reduced voltage noise. Clock signals may be provided to semiconductor devices, and may be distributed throughout the device. Drivers are provided along signal paths within the device which may act as buffers for the clock signals. Each clock signal may be coupled to multiple driver circuits within the driver. Each of the multiple driver circuits may be coupled to a different pair of power supply voltage lines. The driver circuits may all have a similar delay to each other.Type: GrantFiled: September 27, 2018Date of Patent: December 31, 2019Assignee: Micron Technology, Inc.Inventor: Kazuyuki Morishige
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Patent number: 8053813Abstract: A semiconductor device includes first lines extending in a first direction and formed in a first wiring layer in a predetermined arrangement order, second lines formed in a second wiring layer different from the first wring layer in the predetermined arrangement order, and contacts electrically connecting between the first lines and the second lines so as to match the arrangement order. In the semiconductor device, at least adjacent two tracks are defined in a linear manner parallel to a second direction perpendicular to the first direction. Then, each of the second lines includes a first line portion extending along one of the two tracks, a second line portion extending along another of the two tracks, and a connection portion connecting between the first and second line portions, while two or more of the contacts are formed at the connection portion.Type: GrantFiled: February 4, 2009Date of Patent: November 8, 2011Assignee: Elpida Memory, Inc.Inventor: Kazuyuki Morishige
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Publication number: 20090200579Abstract: A semiconductor device includes first lines extending in a first direction and formed in a first wiring layer in a predetermined arrangement order, second lines formed in a second wiring layer different from the first wring layer in the predetermined arrangement order, and contacts electrically connecting between the first lines and the second lines so as to match the arrangement order. In the semiconductor device, at least adjacent two tracks are defined in a linear manner parallel to a second direction perpendicular to the first direction. Then, each of the second lines includes a first line portion extending along one of the two tracks, a second line portion extending along another of the two tracks, and a connection portion connecting between the first and second line portions, while two or more of the contacts are formed at the connection portion.Type: ApplicationFiled: February 4, 2009Publication date: August 13, 2009Applicant: Elpida Memory, Inc.Inventor: Kazuyuki Morishige
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Publication number: 20060119371Abstract: An evaluation circuit includes an evaluation pad and a first inverter circuit connected to a first measurement point and a second measurement point to be jointed to first and second power sources, respectively. The first inverter circuit is initialized by an initialization signal from the evaluation pad. The first inverter circuit selectively outputs electric potentials of the first and the second measurement points to the evaluation pad. The circuit further includes a second inverter circuit which has an input connected to the evaluation pad and an output connected to the first inverter circuit. The first and the second inverter circuits are connected in the form of a loop. According to the present invention, the number of evaluation pads can be reduced.Type: ApplicationFiled: November 9, 2005Publication date: June 8, 2006Inventor: Kazuyuki Morishige