Abstract: An output circuit includes an output block and a predrive block for driving the output block based on an input signal. The predrive block has a clamp unit connected between the gate terminal of a first output transistor and the gate terminal of a second output transistor to limit the potential of the gate terminal of the first output transistor to a value of not more than a first potential and limit the potential of the gate terminal of the second output transistor to a value of not less than a second potential.

Abstract: An output circuit includes an output block and a predrive block for driving the output block based on an input signal. The predrive block has a clamp unit connected between the gate terminal of a first output transistor and the gate terminal of a second output transistor to limit the potential of the gate terminal of the first output transistor to a value of not more than a first potential and limit the potential of the gate terminal of the second output transistor to a value of not less than a second potential.

Abstract: A level shift circuit has a driving circuit and an output circuit. The driving circuit has a clamp circuit for receiving first and second bias potentials, outputting first and second drive signals which are not less than a reference potential, less than the first bias potential, and complementary to each other, and also outputting third and fourth drive signals which are higher than the second bias potential, not more than a power source potential, and complementary to each other. The output circuit has a first output transistor of a first conductivity type and a second output transistor of a second conductivity type which are connected in series to each other. The first output transistor has a gate for receiving the first drive signal and one electrode for receiving the reference potential. The second output transistor has a gate for receiving the third drive signal and one electrode for receiving the power source potential.

Abstract: A level shift circuit has a driving circuit and an output circuit. The driving circuit has a clamp circuit for receiving first and second bias potentials, outputting first and second drive signals which are not less than a reference potential, less than the first bias potential, and complementary to each other, and also outputting third and fourth drive signals which are higher than the second bias potential, not more than a power source potential, and complementary to each other. The output circuit has a first output transistor of a first conductivity type and a second output transistor of a second conductivity type which are connected in series to each other. The first output transistor has a gate for receiving the first drive signal and one electrode for receiving the reference potential. The second output transistor has a gate for receiving the third drive signal and one electrode for receiving the power source potential.

Abstract: A switching power supply circuit in accordance with the present invention is configured such that a switched-capacitor circuit is provided between an output terminal for outputting an output voltage and an input of an error amplification circuit, the output signal from the error amplification circuit for amplifying the error between a DC output voltage and a reference voltage is compared with a reference signal by a pulse width modulation circuit, and a voltage conversion section is turned ON/OFF continuously using the output signal of a pulse width modulation circuit while having a predetermined period with respect to an input voltage.