Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.

Abstract: Inspection wire is formed along at least a portion of the outer periphery of, and preferably along the entire perimeter of, a chip area enclosed by scribe areas, using an arbitrary wiring layer, conductive material, or diffusion layer of the semiconductor chip, and the opposite ends of the inspection wire are connected, via a wiring layer and contact plugs, to pads on the semiconductor chip, either directly or via prescribed switching means. By measuring the resistance of the inspection wire before and after dicing using the pads, chips and cracks occurring during dicing of the semiconductor chip, as well as chipping which progresses in subsequent packaging and assembly processes, or due to the application of stress, shocks, thermal cycles or similar after incorporation into products, can be detected.

Abstract: Scribe lines demarcating semiconductor chips comprise, in both the vertical direction and the horizontal direction, first-type scribe lines of the minimum width enabling cutting by dicing or other means, and second-type scribe lines enabling placement of TEGs, alignment marks or other accessories, and a placement pattern is set so that a unit cell which can be exposed in a single shot comprises one second-type scribe line. By this means, the area occupied by scribe lines can be reduced. Further, by decreasing the number of placement of semiconductor chips constituting a unit cell, and by cutting substantially along the center line of second-type scribe lines, the shapes of scribe lines on the periphery of semiconductor chips can be changed, so that the position in the unit cell can be determined.

Abstract: A semiconductor chip is composed of first and second contact pads; a first latch circuit connected with the first contact pad; a second latch circuit connected with the second contact pads; an internal circuit electrically connected with the first and second latch circuits; and a control circuit controlling data transfer between the first and second latch circuits. The area of the first contact pad is larger than that of the second contact pad.

Abstract: A semiconductor circuit is installed on a printed circuit board having a power wiring pattern and a ground wiring pattern that do not intersect. The semiconductor circuit includes a first power supply terminal and a first ground terminal for a first side of the semiconductor circuit, and a second power supply terminal and a second ground terminal for a second side opposing to the first side. The direction from the first power supply terminal to the first ground terminal is the same as the direction from the second power supply terminal to the second ground terminal.

Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.

Abstract: A microcomputer chip includes a plurality of first electrode pads arranged in a chip circumferential section; a plurality of second electrode pads arranged inside from the plurality of first electrode pads; and an emulation circuit connected with the plurality of second electrode pads to interface with an external unit in emulation. The plurality of second electrode pads may be arranged on an area where a functional circuit is formed.

Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.

Abstract: A microcomputer includes a circuit block; a nonvolatile memory configured to store optimization data for optimization of an operation of the microcomputer; and an optimization circuit configured to read out memory optimization data as a part of the optimization data from the nonvolatile memory in synchronization with a first frequency clock signal as an first clock signal to optimize an operation of the nonvolatile memory, and then to read out circuit block optimization data as another part of the optimization data from the nonvolatile memory in synchronization with a second frequency clock signal as the first clock signal to optimize an operation of the circuit block. The frequency of the first frequency clock signal is lower than that of the second frequency clock signal.

Abstract: A semiconductor circuit is installed on a printed circuit board having a first wiring pattern and a second wiring pattern. The semiconductor circuit includes a first power supply terminal and a first ground terminal which are provided for a first side of the semiconductor circuit. The first power supply terminal is connected with the first wiring pattern. The first ground terminal is connected with the second wiring pattern. A second power supply terminal and a second ground terminal are provided for a second side opposing to the first side. The second power supply terminal is connected with the first wiring pattern and the second ground terminal is connected with the second wiring pattern. The first and second power and ground terminals are arranged such that the first wiring pattern and the second wiring pattern do not intersect in a region of the wiring substrate corresponding to the semiconductor circuit.

Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.

Abstract: A microcomputer includes a circuit block; a nonvolatile memory configured to store optimization data for optimization of an operation of the microcomputer; and an optimization circuit configured to read out memory optimization data as a part of the optimization data from the nonvolatile memory in synchronization with a first frequency clock signal as an first clock signal to optimize an operation of the nonvolatile memory, and then to read out circuit block optimization data as another part of the optimization data from the nonvolatile memory in synchronization with a second frequency clock signal as the first clock signal to optimize an operation of the circuit block. The frequency of the first frequency clock signal is lower than that of the second frequency clock signal.

Abstract: A semiconductor chip is composed of first and second contact pads; a first latch circuit connected with the first contact pad; a second latch circuit connected with the second contact pads; an internal circuit electrically connected with the first and second latch circuits; and a control circuit controlling data transfer between the first and second latch circuits. The area of the first contact pad is larger than that of the second contact pad.

Abstract: A microcomputer chip includes a plurality of first electrode pads arranged in a chip circumferential section; a plurality of second electrode pads arranged inside from the plurality of first electrode pads; and an emulation circuit connected with the plurality of second electrode pads to interface with an external unit in emulation. The plurality of second electrode pads may be arranged on an area where a functional circuit is formed.

Abstract: Scribe lines demarcating semiconductor chips comprise, in both the vertical direction and the horizontal direction, first-type scribe lines of the minimum width enabling cutting by dicing or other means, and second-type scribe lines enabling placement of TEGs, alignment marks or other accessories, and a placement pattern is set so that a unit cell which can be exposed in a single shot comprises one second-type scribe line. By this means, the area occupied by scribe lines can be reduced. Further, by decreasing the number of placement of semiconductor chips constituting a unit cell, and by cutting substantially along the center line of second-type scribe lines, the shapes of scribe lines on the periphery of semiconductor chips can be changed, so that the position in the unit cell can be determined.

Abstract: Inspection wire is formed along at least a portion of the outer periphery of, and preferably along the entire perimeter of, a chip area enclosed by scribe areas, using an arbitrary wiring layer, conductive material, or diffusion layer of the semiconductor chip, and the opposite ends of the inspection wire are connected, via a wiring layer and contact plugs, to pads on the semiconductor chip, either directly or via prescribed switching means. By measuring the resistance of the inspection wire before and after dicing using the pads, chips and cracks occurring during dicing of the semiconductor chip, as well as chipping which progresses in subsequent packaging and assembly processes, or due to the application of stress, shocks, thermal cycles or similar after incorporation into products, can be detected.

Abstract: Longitudinal facing laid on a base between retainers at a prescribed spacing includes a central face plate, an inner riser along right and left edges of the face plate, an outer riser on an outer side of each inner riser, a drain channel formed between the inner and outer risers, an engaging portion at at least one of end and median portions of the outer riser and in resilient engagement with the retainers.

Abstract: A microcomputer performs serial data transfer for a peripheral device in synchronism with machine cycles of the CPU without requesting an interrupt routine of the CPU. The microcomputer incorporates an improved serial data communication unit having a serial data terminal and a serial clock terminal coupled to the peripheral device. The CPU supplies a transfer start command to the serial data communication unit when it executes a serial data communication instruction. A serial clock control circuit in the serial data communication unit responds to the transfer start command to supply the clock terminal with a serial clock signal having the same frequency as the clock signal of the CPU in synchronism with the beginning of a certain machine cycle.

Abstract: A video display control circuit includes a reading circuit for reading address data in a video RAM pointer. The video RAM pointer designates an address in a RAM where an address data to be supplied to a character ROM pointer is stored. The character ROM pointer designates an address in a ROM where character data by which characters are displayed on a screen are stored. If the address data read from the video RAM pointer is earlier in access time than a selected address of the video RAM, into which a new address data is required to be re-written, operation of re-writing data of the video RAM is not carried out, so that flickering or momentary black-out of the display caused by the re-writing operation may not occur.

Abstract: A synergistic germicidal composition includes a derivative of .alpha.