Patents by Inventor Kazuyuki Noshita

Kazuyuki Noshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having chip scale package
    Patent number: 6656766
    Abstract: A first surface of a semiconductor chip and an upper surface of a circuit board are bonded with a pad of the semiconductor chip fitted to a first opening of the circuit board. The pad is electrically connected to a wire of the circuit board. The pad is sealed with a first resin. A second resin is disposed on the upper surface of the circuit board. A second resin includes an upper surface at a height substantially equal to a height of a second surface of the semiconductor chip at a point apart from a corner of a square of the first surface of the semiconductor chip.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: December 2, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuyuki Noshita
  • Semiconductor device having chip scale package
    Publication number: 20030094681
    Abstract: A first surface of a semiconductor chip and an upper surface of a circuit board are bonded with a pad of the semiconductor chip fitted to a first opening of the circuit board. The pad is electrically connected to a wire of the circuit board. The pad is sealed with a first resin. A second resin is disposed on the upper surface of the circuit board. A second resin includes an upper surface at a height substantially equal to a height of a second surface of the semiconductor chip at a point apart from a corner of a square of the first surface of the semiconductor chip.
    Type: Application
    Filed: January 7, 2003
    Publication date: May 22, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kazuyuki Noshita
  • Semiconductor device having chip scale package
    Patent number: 6525412
    Abstract: A first surface of a semiconductor chip and an upper surface of a circuit board are bonded with a pad of the semiconductor chip fitted to a first opening of the circuit board. The pad is electrically connected to a wire of the circuit board. The pad is sealed with a first resin. A second resin is disposed on the upper surface of the circuit board. A second resin includes an upper surface at a height substantially equal to a height of a second surface of the semiconductor chip at a point apart from a corner of a square of the first surface of the semiconductor chip.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: February 25, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuyuki Noshita
  • Semiconductor device having chip scale package
    Publication number: 20020063264
    Abstract: A first surface of a semiconductor chip and an upper surface of a circuit board are bonded with a pad of the semiconductor chip fitted to a first opening of the circuit board. The pad is electrically connected to a wire of the circuit board. The pad is sealed with a first resin. A second resin is disposed on the upper surface of the circuit board. A second resin includes an upper surface at a height substantially equal to a height of a second surface of the semiconductor chip at a point apart from a corner of a square of the first surface of the semiconductor chip.
    Type: Application
    Filed: November 30, 2001
    Publication date: May 30, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kazuyuki Noshita