Patents by Inventor Kazuyuki Omori

Kazuyuki Omori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8227880
    Abstract: To provide a semiconductor device capable of write operation to a selected magnetoresistive element without causing a malfunction of a non-selected magnetoresistive element and a manufacturing method of this semiconductor device. The semiconductor device includes a magnetic storage element having a magnetization free layer whose magnetization direction is made variable and formed over a lead interconnect and a digit line located below the magnetic storage element, extending in a first direction, and capable of changing the magnetization state of the magnetization free layer by the magnetic field generated. The digit line includes an interconnect body portion and a cladding layer covering therewith the bottom surface and the side surface of the interconnect body portion and opened upward. The cladding layer includes a sidewall portion covering therewith the side surface of the interconnect body portion and a bottom wall portion covering therewith the bottom surface of the interconnect body portion.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: July 24, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Mikio Tsujiuchi, Yosuke Takeuchi, Kazuyuki Omori, Kenichi Mori
  • Patent number: 8125085
    Abstract: A semiconductor device includes an interlayer film formed over a semiconductor substrate. A groove is formed in the interlayer film. A wiring formed in the groove is a copper alloy including copper and a metal element. An oxide layer of the metal element is formed over the surface of the wiring. The oxide layer is formed in a first region along a grain boundary of a copper crystal and a second region surrounded by the grain boundary, over the surface of the wiring. The oxide layer formed in the first region has a thickness greater than that of the oxide layer formed in the second region.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: February 28, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyoshi Maekawa, Kenichi Mori, Kazuyuki Omori, Yuki Koyama
  • Publication number: 20120043630
    Abstract: In MRAM, a write wiring clad in a ferromagnetic film has been used to reduce a write current or avoid disturbances. Besides, a CuAl wiring obtained by adding a trace of Al to a Cu wiring has been used widely to secure reliability of a high reliability product. There is a high possibility of MRAM being mounted in high reliability products so that reliability is important. Clad wiring however increases the resistance of the CuAl wiring, which is originally high, so that using both may fail to satisfy the specification of the wiring resistance. In the semiconductor device of the invention having plural copper-embedded wiring layers, copper wiring films of plural copper-embedded clad wirings configuring a memory cell matrix region of MRAM are made of relatively pure copper, while a CuAl wiring film is used as copper wiring films of copper-embedded non-clad wirings below these wiring layers.
    Type: Application
    Filed: July 13, 2011
    Publication date: February 23, 2012
    Inventors: Kazuyuki OMORI, Kenichi Mori, Naohito Suzumura
  • Publication number: 20110298070
    Abstract: A semiconductor device has a magnetoresistive element, a bit line over the magnetoresistive element, and a yoke cover over the bit line. To form the yoke cover, a laminate film is first formed over the bit line, the laminate film having a first barrier metal layer, a magnetic layer, and a second barrier metal layer which are formed successively over the bit line. Then, the laminate film is subjected to: reactive ion etching with a gas mixture of a carbon tetrafluoride (CF4) gas and an argon (Ar) gas, reactive ion etching with a gas mixture of carbon monoxide (CO), an ammonia (NH3) gas, and an argon (Ar) gas, and reactive ion etching with a gas mixture of a carbon tetrafluoride (CF4) gas and an argon (Ar) gas.
    Type: Application
    Filed: June 1, 2011
    Publication date: December 8, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Shoichi Fukui, Satoshi Iida, Shinroku Maejima, Kazuyuki Omori
  • Publication number: 20110062539
    Abstract: To provide a semiconductor device in which the deterioration of the rewrite property is suppressed. In a memory cell region, magnetoresistive elements in a semiconductor magnetic-storage device are formed in an array shape in a mode that the magnetoresistive elements are arranged at portions where digit lines extending in one direction intersect bit lines extending in the direction approximately orthogonal to the digit lines. The digit line and the bit line have such a wiring structure constituted by covering a copper film to be a wiring main body with a cladding layer. One end side of the magnetoresistive element is electrically coupled to the bit line via a top via formed from a non-magnetic material.
    Type: Application
    Filed: September 17, 2010
    Publication date: March 17, 2011
    Inventors: Ryoji MATSUDA, Motoi Ashida, Shuichi Ueno, Shoichi Fukui, Shinya Hirano, Seiji Muranaka, Kazuyuki Omori
  • Publication number: 20110057275
    Abstract: To provide a semiconductor device capable of write operation to a selected magnetoresistive element without causing a malfunction of a non-selected magnetoresistive element and a manufacturing method of this semiconductor device. The semiconductor device includes a magnetic storage element having a magnetization free layer whose magnetization direction is made variable and formed over a lead interconnect and a digit line located below the magnetic storage element, extending in a first direction, and capable of changing the magnetization state of the magnetization free layer by the magnetic field generated. The digit line includes an interconnect body portion and a cladding layer covering therewith the bottom surface and the side surface of the interconnect body portion and opened upward. The cladding layer includes a sidewall portion covering therewith the side surface of the interconnect body portion and a bottom wall portion covering therewith the bottom surface of the interconnect body portion.
    Type: Application
    Filed: September 2, 2010
    Publication date: March 10, 2011
    Inventors: Mikio TSUJIUCHI, Yosuke Takeuchi, Kazuyuki Omori, Kenichi Mori
  • Publication number: 20100044864
    Abstract: The present invention aims at providing a method of manufacturing a semiconductor device capable of suppressing metal diffusion from the upper face of wiring. In the present invention, a copper seed film containing copper and a first metal element is formed in a groove formed in a first interlayer film over a semiconductor substrate. After that, a copper plating treatment is performed. After that, a first heat treatment is performed in a first atmosphere in which the copper layer is not oxidized. Then, an excess metal layer of copper alloy is removed and copper alloy wiring is formed in the groove. After that, a second heat treatment is performed in a second atmosphere containing oxygen to form an oxide layer being the oxide of the first metal element over the surface of the copper alloy wiring.
    Type: Application
    Filed: June 9, 2009
    Publication date: February 25, 2010
    Inventors: Kazuyoshi MAEKAWA, Kenichi Mori, Kazuyuki Omori, Yuki Koyama
  • Patent number: 6658023
    Abstract: An image transmission system in which when each of a plurality of image signals is transformed into compressed image data compressed at an image compressing portion, the image data are assembled to cells at a cell assembly portion, and the cells from the cell assembly portion are switched at a switching portion, a band controller controls the cell assembly portion so that a band of a transmission line has a value lower than a total band required for a simultaneous transmission of each of the image data. Also, a network controller for controlling band controllers or compression rate controllers at each of communication nodes on a network is provided. Moreover, a sensor which detects a change of an event to control the band controller or the compression rate controller is provided.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: December 2, 2003
    Assignee: Fujitsu Limited
    Inventors: Kazuyuki Omori, Hiroyuki Hatta
  • Patent number: 5739623
    Abstract: A vibration wave driven motor including a stator, a rotor, and an urging member for causing the stator and the rotor to contact each other under pressure. The urging member is supported by a supporting member at a predetermined position. The supporting member is shiftable in the urging direction of the urging member.
    Type: Grant
    Filed: June 23, 1995
    Date of Patent: April 14, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hajime Kanazawa, Tetsuya Nishio, Kazuki Fujimoto, Kazuyuki Omori