Abstract: Disclosed is a metal pipe which is for vehicle piping and which exhibits high corrosion resistance without the corrosion resistance being strengthened by means of a coating or a resin coating-layer, due to a hot-dip plating coating-layer being formed by applying a hot-dip plating to the pipe. The disclosed metal pipe for vehicle piping has a plating coating-layer formed on the surface of a formed metal pipe, said plating coating-layer being formed by means of hot-dip plating on the surface of the metal pipe, and the plating coating-layer being formed from a hot-dip plating alloy comprising at least 3 weight % Al, 1-15 weight % Mg, and Zn and unavoidable impurities as the remainder.

Abstract: In a reception apparatus 1, a multiphase sampling clock signal is generated by a sampling clock signal generation circuit 40, based on a clock signal which has been phase-adjusted by a phase adjustment circuit 50. The data of each of the bits of a serial data signal is sampled and output by a sampler block circuit 30n, with timing indicated by the sampling clock signal. The amount of phase adjustment of the clock signal in the phase adjustment circuit 50 is set such that the delay time from generation of the multiphase sampling clock signal in the sampling clock signal generation circuit 40 until indication of the sampling timing by the sampling clock signal in the sampler block circuit 30n is canceled.

Abstract: In a reception apparatus 1, a multiphase sampling clock signal is generated by a sampling clock signal generation circuit 40, based on a clock signal which has been phase-adjusted by a phase adjustment circuit 50. The data of each of the bits of a serial data signal is sampled and output by a sampler block circuit 30n, with timing indicated by the sampling clock signal. The amount of phase adjustment of the clock signal in the phase adjustment circuit 50 is set such that the delay time from generation of the multiphase sampling clock signal in the sampling clock signal generation circuit 40 until indication of the sampling timing by the sampling clock signal in the sampler block circuit 30n is canceled.

Abstract: A voltage controlled oscillator 8 is configured to include a plurality of variable delay circuits 30 that are connected to one another so as to form a ring. Output fixing units 31 each of which fixes, when the voltage controlled oscillator 8 stops operating, the output of a corresponding one of the variable delay circuits 30 are provided. As a result, even if the voltage controlled oscillator 8 that operates by following the frequency of an input clock has changed into an operation stop state, because the output fixing units 31 fix the outputs of the variable delay circuits 30, the output of the voltage controlled oscillator 8 is prevented from being in an inconstant state. Thus, it is possible to ensure that the voltage controlled oscillator 8 oscillates properly when the voltage controlled oscillator 8 resumes or starts its operation.

Abstract: A steel pipe for use in a piping of an automobile is provided, which can exhibit enhanced corrosion resistance and resistance to chipping required for a steel pipe for use in a vehicle, such as a fuel piping or brake piping, without need of employing a thicker protective resin coating layer as well as provide excellent formability for processing an end portion of the pipe. In a steel pipe which is coated with a multilayered coating including a plated coating, the multilayered coating comprises a hot dipped coating 12, a chemical conversion coating 14 provided as an outer layer of the hot dipped coating, and an outermost thin PA resin coating 18.

Abstract: A voltage controlled oscillator 8 is configured to include a plurality of variable delay circuits 30 that are connected to one another so as to form a ring. Output fixing units 31 each of which fixes, when the voltage controlled oscillator 8 stops operating, the output of a corresponding one of the variable delay circuits 30 are provided. As a result, even if the voltage controlled oscillator 8 that operates by following the frequency of an input clock has changed into an operation stop state, because the output fixing units 31 fix the outputs of the variable delay circuits 30, the output of the voltage controlled oscillator 8 is prevented from being in an inconstant state. Thus, it is possible to ensure that the voltage controlled oscillator 8 oscillates properly when the voltage controlled oscillator 8 resumes or starts its operation.

Abstract: A semiconductor integrated circuit with stabilized amplitude and offset potential of output signals comprising an output circuit including plural transistors supplied with differential signals, for performing switching operation. A first transistor is connected between a first power supply potential and the output circuit. A second transistor is connected between the output circuit and a second power supply potential. A third transistor is connected to the first power supply potential. A fourth transistor, passes a current proportional to that flowing in the second transistor. A differential amplifier controls gate potentials of the first and third transistors such that a potential at a connection point between a first resistance and a second resistance approaches a predetermined potential.

Abstract: A semiconductor integrated circuit capable of stabilizing the amplitude and the offset potential of the output signals without increasing the number of operational amplifiers in a line driver for outputting small-amplitude differential signals to external.

Abstract: A barrel shifter is provided with a plurality of shifters arranged in series for combining pieces of data A, B respectively represented by a sequence of 32-bit, 16-bit, or 8-bit binary digits into a piece of combined data C and shifting the combined data C by some bits. The shifters consists of a 16-bit shifter, 8-bit shifter, 4-bit shifter, 2-bit shifter, and two 1-bit shifters. The 32-bit data A, B are shifted in the 16-bit shifter. The 16-bit data B is shifted in the 16-bit shifter to connect with the 16-bit data A. The 8-bit data B is shifted in the 16-bit shifter to approach the 8-bit data B. The combined data C formed by connecting the 32-bit data A, B or the 16-bit data A, B in the 16-bit shifter is shifted in the following shifters. The 8-bit data B in the 16-bit shifter is shifted in the 8-bit shifter to connect with the 8-bit data A so that the combined data C is formed. The combined data C formed by connecting the 8-bit data A, B in the 8-bit shifter is shifted in the following shifters.

Abstract: A barrel shifter for successively shifting reference data in a plurality of stages includes a wiring network for every stage to shift the reference data to produce shifted data and selectors connected to the wiring network for every stage except for a specific stage to output either the reference data or the shifted data as new reference data to a following stage while distorting the electric waveform of the selected data. The barrel shifter also includes complex clocked inverters connected to the wiring network in the specific stage to output either the reference data or the shifted data as new reference data to a following stage while correcting the electric waveform of the selected data.

Abstract: A bus driver in which at least two P channel MOS transistors and at least two N channel MOS transistors are employed and these are respectively connected in series. A data signal is inputted into a gate of one of the P channel MOS transistors, an inverted input of an enable signal is inputted into a gate of the other of the P channel MOS transistors, the enable signal is inputted into a gate of one of the N channel MOS transistors and the data signal is also inputted into a gate of the other of the N channel MOS transistors. Further, an output signal is outputted from a connection point of the P channel MOS transistors and the N channel MOS transistors. Also disclosed is another embodiment of a bus driver in which an inverted signal of an enable signal is inputted into the other of the P channel MOS transistors through an inverter.

Abstract: An integrated standard cell consisting of a plurality of standard cells each having a logical area, at least one power supply line, and one ground line, which further includes two clock signal lines for supplying clock signals. These signals are formed within each standard cell and are provided outside of the power supply line and the ground line, in parallel thereto. The two clock signal lines are connected to the logical area through each shunt line which substantially extends in the vertical direction to the clock signal lines. With this construction, a quantitative prediction for the time delay of clock signals which propagate in the clock signal lines becomes easy, thereby preventing any skew of the clock signals from occurring.