Patents by Inventor Kazuyuki Onoe
Kazuyuki Onoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128724Abstract: An optical semiconductor device according to the present disclosure includes: a first-conductivity-type semiconductor substrate having a projecting portion; second-conductivity-type intermediate layers formed on both sides of the projecting portion above the semiconductor substrate; a stripe-shaped mesa structure formed of a first-conductivity-type first cladding layer, an active layer, and a second-conductivity-type second cladding layer, which are laminated above a surface including a top of the projecting portion so as to be centered at the projecting portion; buried layers formed on both sides of the mesa structure, to block current; and a second-conductivity-type contact layer formed at surfaces of the mesa structure and the buried layers.Type: ApplicationFiled: March 5, 2021Publication date: April 18, 2024Applicant: Mitsubishi Electric CorporationInventors: Kazuyuki ONOE, Tsutomu YAMAGUCHI, Yohei HOKAMA
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Patent number: 11616342Abstract: A semiconductor optical element includes a first cladding layer; a second cladding layer formed in a ridge shape; and optical confinement layer interposed between the first cladding layer and the second cladding layer to propagate light, wherein the second cladding layer is configured with a ridge bottom layer; a ridge intermediate layer; and a ridge top layer in this order from the optical confinement layer, and the ridge intermediate layer is formed wider in cross section perpendicular to the optical axis—the light propagating direction in optical confinement layer—than the ridge bottom layer and the ridge top layer.Type: GrantFiled: April 2, 2018Date of Patent: March 28, 2023Assignee: Mitsubishi Electric CorporationInventors: Tsutomu Yamaguchi, Hitoshi Sakuma, Kazuyuki Onoe
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Patent number: 11448905Abstract: A semiconductor device according to the present invention includes a substrate, an active layer provided on the substrate, a cladding layer provided on the active layer, a contact layer provided on the cladding layer, the contact layer having an upper surface, a back surface which is a surface on an opposite side to the upper surface, and a side surface connecting the upper surface and the back surface, the contact layer is larger in width than the cladding layer; and an electrode that is in contact with the upper surface of the contact layer and the side surface of the contact layer from an upper end to a lower end of the side surface of the contact layer.Type: GrantFiled: November 17, 2017Date of Patent: September 20, 2022Assignee: Mitsubishi Electric CorporationInventor: Kazuyuki Onoe
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Publication number: 20220294187Abstract: A semiconductor device according to the present disclosure includes a main part that includes a semiconductor substrate, a first cladding layer provided on the semiconductor substrate, an active layer provided on the first cladding layer, and a second cladding layer provided on the active layer, and in which a flat part and a mesa part are formed, the mesa part including the active layer and a first embedded layer covering a top surface of the flat part and a side surface of the mesa part, wherein the first embedded layer has a projecting part on a top surface of a portion provided in a region within a height of the mesa part from a boundary between the mesa part and the flat part in the top surface of the flat part.Type: ApplicationFiled: January 22, 2020Publication date: September 15, 2022Applicant: Mitsubishi Electric CorporationInventor: Kazuyuki ONOE
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Publication number: 20210075194Abstract: A semiconductor optical element includes a first cladding layer; a second cladding layer formed in a ridge shape; and optical confinement layer interposed between the first cladding layer and the second cladding layer to propagate light, wherein the second cladding layer is configured with a ridge bottom layer; a ridge intermediate layer; and a ridge top layer in this order from the optical confinement layer, and the ridge intermediate layer is formed wider in cross section perpendicular to the optical axis—the light propagating direction in optical confinement layer—than the ridge bottom layer and the ridge top layer.Type: ApplicationFiled: April 2, 2018Publication date: March 11, 2021Applicant: Mitsubishi Electric CorporationInventors: Tsutomu YAMAGUCHI, Hitoshi SAKUMA, Kazuyuki ONOE
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Publication number: 20200333638Abstract: A semiconductor device according to the present invention includes a substrate, an active layer provided on the substrate, a cladding layer provided on the active layer, a contact layer provided on the cladding layer, the contact layer having an upper surface, a back surface which is a surface on an opposite side to the upper surface, and a side surface connecting the upper surface and the back surface, the contact layer is larger in width than the cladding layer; and an electrode that is in contact with the upper surface of the contact layer and the side surface of the contact layer from an upper end to a lower end of the side surface of the contact layer.Type: ApplicationFiled: November 17, 2017Publication date: October 22, 2020Applicant: Mitsubishi Electric CorporationInventor: Kazuyuki ONOE
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Patent number: 10248023Abstract: A method of manufacturing a semiconductor device includes: coating a first resist containing a photoacid generator or a thermal acid generator on a semiconductor substrate; forming a first opening portion in the first resist by optical exposure; subjecting a shrink agent containing an acid to a crosslinking reaction by the heat treatment to form a thermoset layer on an overall surface of the first resist; coating a second resist on the semiconductor substrate and the thermoset layer; and forming a second opening portion located above the first opening portion and larger than the first opening portion in the second resist by optical exposure.Type: GrantFiled: February 19, 2018Date of Patent: April 2, 2019Assignee: Mitsubishi Electric CorporationInventors: Yasuki Aihara, Kazuyuki Onoe, Takahiro Ueno
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Publication number: 20190079400Abstract: A method of manufacturing a semiconductor device includes: coating a first resist containing a photoacid generator or a thermal acid generator on a semiconductor substrate; forming a first opening portion in the first resist by optical exposure; subjecting a shrink agent containing an acid to a crosslinking reaction by the heat treatment to form a thermoset layer on an overall surface of the first resist; coating a second resist on the semiconductor substrate and the thermoset layer; and forming a second opening portion located above the first opening portion and larger than the first opening portion in the second resist by optical exposure.Type: ApplicationFiled: February 19, 2018Publication date: March 14, 2019Applicant: Mitsubishi Electric CorporationInventors: Yasuki AIHARA, Kazuyuki ONOE, Takahiro UENO
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Patent number: 9805978Abstract: A method of manufacturing a semiconductor device includes: forming a resist separation layer on a first main surface of a SiC substrate; applying a resist retaining a shape at a temperature of 200° C. or higher on the resist separation layer; patterning the resist by photolithography; heating a stage an which the SiC substrate is placed to a temperature of 200° C. or higher by a temperature control function, and dry-etching the SiC substrate by using the patterned resist as a mask to form a via hole; and after forming the via hole, removing the resist separation layer to separate the resist from the SiC substrate.Type: GrantFiled: October 31, 2016Date of Patent: October 31, 2017Assignee: Mitsubishi Electric CorporationInventors: Kohei Miki, Kazuyuki Onoe, Shinichi Miyakuni
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Patent number: 9773703Abstract: A method of manufacturing a semiconductor device includes: forming a resist separation layer on a first main surface of a SiC substrate; applying a resist retaining a shape at a temperature of 200° C. or higher on the resist separation layer; patterning the resist by photolithography; heating a stage an which the SiC substrate is placed to a temperature of 200° C. or higher by a temperature control function, and dry-etching the SiC substrate by using the patterned resist as a mask to form a via hole; and after forming the via hole, removing the resist separation layer to separate the resist from the SiC substrate.Type: GrantFiled: October 31, 2016Date of Patent: September 26, 2017Assignee: Mitsubishi Electric CorporationInventors: Kohei Miki, Kazuyuki Onoe, Shinichi Miyakuni
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Publication number: 20170162439Abstract: A method of manufacturing a semiconductor device includes: forming a resist separation layer on a first main surface of a SiC substrate; applying a resist retaining a shape at a temperature of 200° C. or higher on the resist separation layer; patterning the resist by photolithography; heating a stage an which the SiC substrate is placed to a temperature of 200° C. or higher by a temperature control function, and dry-etching the SiC substrate by using the patterned resist as a mask to form a via hole; and after forming the via hole, removing the resist separation layer to separate the resist from the SiC substrate.Type: ApplicationFiled: October 31, 2016Publication date: June 8, 2017Applicant: Mitsubishi Electric CorporationInventors: Kohei MIKI, Kazuyuki ONOE, Shinichi MIYAKUNI
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Patent number: 8524601Abstract: A method of manufacturing a semiconductor device includes forming an insulating film on a surface of a semiconductor layer, forming a resist on a surface of the insulating film, the resist having an opening, forming a hardened layer on an inner circumference of the resist by attaching a pattern shrinking agent to the resist, the pattern shrinking agent undergoing a cross-linking reaction with the resist, etching the insulating film using the resist and the hardened layer as masks, removing the hardened layer, and forming a metal layer on a surface of the semiconductor layer, on a surface of the insulating film, and on a surface of the resist. The method further includes removing the resist and the portion of the metal layer on the surface of the resist by lift-off.Type: GrantFiled: December 22, 2011Date of Patent: September 3, 2013Assignee: Mitsubishi Electric CorporationInventors: Kenichiro Kurahashi, Hidetoshi Koyama, Kazuyuki Onoe
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Publication number: 20120208365Abstract: A method of manufacturing a semiconductor device includes forming an insulating film on a surface of a semiconductor layer, forming a resist on a surface of the insulating film, the resist having an opening, forming a hardened layer on an inner circumference of the resist by attaching a pattern shrinking agent to the resist, the pattern shrinking agent undergoing a cross-linking reaction with the resist, etching the insulating film using the resist and the hardened layer as masks, removing the hardened layer, and forming a metal layer on a surface of the semiconductor layer, on a surface of the insulating film, and on a surface of the resist. The method further includes removing the resist and the portion of the metal layer on the surface of the resist by lift-off.Type: ApplicationFiled: December 22, 2011Publication date: August 16, 2012Applicant: Mitsubishi Electric CorporationInventors: Kenichiro KURAHASHI, Hidetoshi Koyama, Kazuyuki Onoe