Abstract: In a split-gate-type MONOS memory, increase in a defective rate due to variation in a gate length of a memory gate electrode is prevented, and reliability of a semiconductor device is improved. A first dry etching having a high anisotropic property but a low selection ratio relative to silicon oxide is performed to a silicon film, and then, a second dry etching having a low anisotropic property but a high selection ratio relative to silicon oxide is performed thereto, so that a control gate electrode composed of the silicon film is formed, and then, a sidewall-shaped memory gate electrode is formed on a side surface of the control gate electrode.

Abstract: In a split-gate-type MONOS memory, increase in a defective rate due to variation in a gate length of a memory gate electrode is prevented, and reliability of a semiconductor device is improved. A first dry etching having a high anisotropic property but a low selection ratio relative to silicon oxide is performed to a silicon film, and then, a second dry etching having a low anisotropic property but a high selection ratio relative to silicon oxide is performed thereto, so that a control gate electrode composed of the silicon film is formed, and then, a sidewall-shaped memory gate electrode is formed on a side surface of the control gate electrode.

Abstract: A first etching rate of the first conductive film is calculated by acquiring correlation between an opening ratio of an etching mask and an etching rate of an etching target film, and then, performing a first dry etching to a first conductive film formed on a first wafer. Next, a second etching mask is formed on a second conductive film formed on a second wafer, and an etching time of the second conductive film is determined from the correlation between the opening ratio and the etching rate, the first etching rate, and a film thickness of the second conductive film when the second conductive film is subjected to a second dry etching in time-controlled etching.

Abstract: An asking apparatus includes a load-lock chamber and an apparatus control unit. The load-lock chamber takes in or out a semiconductor wafer to or from a process chamber in which a vacuum process of the semiconductor wafer is performed. The apparatus control unit controls a venting process for putting the load-lock chamber in a vacuum state to an atmospheric state in which the load-lock chamber is opened to atmosphere. Also, the apparatus control unit compares ?1 kPa that is a pressure value previously set and a differential pressure value obtained by subtracting a second pressure value that is a pressure inside the load-lock chamber right after venting to the atmosphere from a first pressure value that is a pressure inside the load-lock chamber right before venting. The apparatus control unit outputs an alarm when the differential pressure value is lower than ?1 kPa that is a pressure value previously set.

Abstract: To improve reliability of a semiconductor manufacturing apparatus using plasma. Moreover, to improve reliability of a semiconductor integrated circuit device and to reduce a fraction defective. A gap between a suction head of an electrostatic chuck and a protection ring is made smaller than a mean free path of molecules of the plasma.

Abstract: A first etching rate of the first conductive film is calculated by acquiring correlation between an opening ratio of an etching mask and an etching rate of an etching target film, and then, performing a first dry etching to a first conductive film formed on a first wafer. Next, a second etching mask is formed on a second conductive film formed on a second wafer, and an etching time of the second conductive film is determined from the correlation between the opening ratio and the etching rate, the first etching rate, and a film thickness of the second conductive film when the second conductive film is subjected to a second dry etching in time-controlled etching.

Abstract: To improve characteristics of a semiconductor device. An element isolation region is etched by using a photoresist film as a mask, and thereby a p-type well that is a layer under the element isolation region is exposed. Thereafter, deposit over a surface of the photoresist film is etched. Then, a source region is formed by implanting impurity ions into the exposed p-type well by using the photoresist film as a mask, and thereafter, the photoresist film is removed. Thereby, it is possible to prevent a hardened layer from being formed due to injection of impurity ions into the deposit over the surface of the photoresist film. As a result, it is possible to suppress a popping phenomenon when the photoresist film is removed, so that it is possible to prevent a pattern of a gate and the like from being broken.

Abstract: When memory cells of EEPROM and a capacitor element are formed on a same semiconductor substrate, the number of processes is prevented from increasing and a manufacturing cost is reduced. Furthermore, reliability of the capacitor element is improved, and characteristics of the memory cells, a MOS transistor, and so on are prevented from changing. A pair of left and right memory cells is formed in a memory cell formation region of a P-type silicon substrate, being symmetrical to each other with respect to a source region, and a capacitor element formed of a lower electrode, a capacitor insulation film, and an upper electrode is formed in a capacitor element formation region of the same P-type silicon substrate. The lower electrode of the capacitor element is formed by patterning a polysilicon film provided for forming control gates of the pair of memory cells.

Abstract: When memory cells of EEPROM and a capacitor element are formed on a same semiconductor substrate, the number of processes is prevented from increasing and a manufacturing cost is reduced. Furthermore, reliability of the capacitor element is improved, and characteristics of the memory cells, a MOS transistor, and so on are prevented from changing. A pair of left and right memory cells is formed in a memory cell formation region of a P-type silicon substrate, being symmetrical to each other with respect to a source region, and a capacitor element formed of a lower electrode, a capacitor insulation film, and an upper electrode is formed in a capacitor element formation region of the same P-type silicon substrate. The lower electrode of the capacitor element is formed by patterning a polysilicon film provided for forming control gates of the pair of memory cells.

Abstract: The invention is directed to a semiconductor integrated circuit device having a plurality of gate insulation films of different thicknesses where reliability of the gate insulation films and characteristics of MOS transistors are improved. A photoresist layer is selectively formed on a SiO2 film in first and third regions, and a SiO2 film in a second region is removed by etching. After the photoresist layer is removed, a silicon substrate is thermally oxidized to form a SiO2 film having a smaller thickness than a first gate insulation film in the second region. Then, the SiO2 film in the third region is removed by etching. After a photoresist layer is removed, the silicon substrate is thermally oxidized to form a SiO2 film having a smaller thickness than a second gate insulation film in the third region.

Abstract: A non-volatile semiconductor memory device includes an interlayer dielectric film 9, 19 flattened by etching back an SOG film. In the non-volatile semiconductor memory device, a barrier film of a silicon nitride film 9D and 19D is formed to cover at least a memory cell composed of a floating gate 4, a control gate 6, etc. Because of such a structure, even if H or OH contained in the SOG is diffused, it will not be trapped by a tunneling film 3. This improves a “trap-up rate”. The barrier film may be formed in only an area covering the memory cell. This reduces its contact area with a tungsten silicide film, thereby suppressing film peeling-off. Thus, the operation life of the memory cell in the non-volatile semiconductor memory device can be improved.