Patents by Inventor Kazuyuki Sakata

Kazuyuki Sakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9905517
    Abstract: Signal transmission characteristics of a semiconductor device are improved. A plurality of wirings of a wiring substrate on which a semiconductor chip is mounted include a first wiring and a second wiring that constitute a differential pair for use in transmitting a differential signal. Moreover, the first wiring and the second wiring respectively have first portions that extend in parallel with each other with a first clearance and second portions that are formed on the same wiring layer as the first portions, and extend in parallel with each other with a second clearance and third portions that are installed between the first portions and the second portions and designed to detour in such directions as to allow the mutual clearance to become greater than the first clearance and the second clearance.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: February 27, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuhiko Hiranuma, Kazuyuki Sakata
  • Patent number: 9673142
    Abstract: A semiconductor device with enhanced reliability. The semiconductor device has a wiring substrate which includes a first terminal electrically connected with a power supply potential supply section of a semiconductor chip, a first wiring coupling the power supply potential supply section with the first terminal, a second terminal electrically connected with a reference potential supply section of the semiconductor chip, and a second wiring coupling the reference potential supply section with the second terminal. The first terminal and second terminal are arranged closer to the periphery of the wiring substrate than the semiconductor chip. The second wiring is extended along the first wiring.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: June 6, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyuki Sakata, Takafumi Betsui
  • Publication number: 20170062322
    Abstract: A semiconductor device with enhanced reliability. The semiconductor device has a wiring substrate which includes a first terminal electrically connected with a power supply potential supply section of a semiconductor chip, a first wiring coupling the power supply potential supply section with the first terminal, a second terminal electrically connected with a reference potential supply section of the semiconductor chip, and a second wiring coupling the reference potential supply section with the second terminal. The first terminal and second terminal are arranged closer to the periphery of the wiring substrate than the semiconductor chip. The second wiring is extended along the first wiring.
    Type: Application
    Filed: July 12, 2016
    Publication date: March 2, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Kazuyuki SAKATA, Takafumi BETSUI
  • Publication number: 20160240487
    Abstract: Signal transmission characteristics of a semiconductor device are improved. A plurality of wirings of a wiring substrate on which a semiconductor chip is mounted include a first wiring and a second wiring that constitute a differential pair for use in transmitting a differential signal. Moreover, the first wiring and the second wiring respectively have first portions that extend in parallel with each other with a first clearance and second portions that are formed on the same wiring layer as the first portions, and extend in parallel with each other with a second clearance and third portions that are installed between the first portions and the second portions and designed to detour in such directions as to allow the mutual clearance to become greater than the first clearance and the second clearance.
    Type: Application
    Filed: January 21, 2016
    Publication date: August 18, 2016
    Inventors: Kazuhiko Hiranuma, Kazuyuki Sakata
  • Publication number: 20150250167
    Abstract: The present invention relates to a composition for noxious organisms-controlling agent having a synergistic effect and a method for using said composition, which comprises, as active ingredients thereof, one or more compounds selected from the phthalamide derivatives represented by general formula (I) being useful as an insecticide or acaricide and one or more compounds selected from the compounds having insecticidal, acaricidal or nematocidal activity: wherein R1, R2 and R3 may be the same or different and each represent hydrogen atom, C3-C6 cycloalkyl, -A1-Qp, etc., each of X and Y may be the same or different and represents hydrogen atom, halogen atom, etc., n is an integer of 1 to 4, m is an integer of 1 to 5, and each of Z1 and Z2 represents O or S.
    Type: Application
    Filed: February 23, 2015
    Publication date: September 10, 2015
    Inventors: Kazuyuki SAKATA, Masayuki MORIMOTO, Hiroshi KODAMA, Tetsuyosi NISHIMATSU
  • Publication number: 20130005712
    Abstract: The present invention relates to a composition for noxious organisms-controlling agent having a synergistic effect and a method for using said composition, which comprises, as active ingredients thereof, one or more compounds selected from the phthalamide derivatives represented by general formula (I) being useful as an insecticide or acaricide and one or more compounds selected from the compounds having insecticidal, acaricidal or nematocidal activity: wherein R1, R2 and R3 may be the same or different and each represent hydrogen atom, C3-C6 cycloalkyl, -A1--Qp, etc., each of X and Y may be the same or different and represents hydrogen atom, halogen atom, etc., n is an integer of 1 to 4, m is an integer of 1 to 5, and each of Z1 and Z2 represents O or S.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 3, 2013
    Inventors: Kazuyuki Sakata, Masayuki Morimoto, Hiroshi Kodama, Tetsuyosi Nishimatsu
  • Patent number: 8329733
    Abstract: The present invention relates to a composition for noxious organisms-controlling agent having a synergistic effect and a method for using said composition, which comprises, as active ingredients thereof, one or more compounds selected from the phthalamide derivatives represented by general formula (I) being useful as an insecticide or acaricide and one or more compounds selected from the compounds having insecticidal, acaricidal or nematocidal activity: wherein R1, R2 and R3 may be the same or different and each represent hydrogen atom, C3-C6 cycloalkyl, -A1-Qp, etc., each of X and Y may be the same or different and represents hydrogen atom, halogen atom, etc., n is an integer of 1 to 4, m is an integer of 1 to 5, and each of Z1 and Z2 represents O or S.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: December 11, 2012
    Assignee: Nihon Nohyaku Co., Ltd.
    Inventors: Kazuyuki Sakata, Masayuki Morimoto, Hiroshi Kodama, Tetsuyosi Nishimatsu
  • Patent number: 8205277
    Abstract: In the upper part and the lower part of a micro-nano bubble generation section 34 in a micro-nano bubble bathtub 1, two kinds of micro-nano bubbles different in a size distribution are generated by first and second micro-nano bubble generators (submerged pump-type micro-nano bubble generator 2 and spiral flow-type micro-nano bubble generator 10) of two kinds, so that bathtub water containing micro-nano bubbles in a wide size distribution can be produced in a large amount. Some of the water containing micro-nano bubbles generated in the lower part is thrown into the first micro-nano bubble generator (spiral flow-type micro-nano bubble generator 10) in the upper part, so that the spiral flow-type micro-nano bubble generator 10 can generate micro-nano bubbles in a smaller size. Therefore, in this bathtub, micro-nano bubbles abundant in size and large in amount can be produced economically.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: June 26, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuyuki Yamasaki, Kazuyuki Sakata, Kazumi Chuhjoh, Masaki Kataoka
  • Patent number: 8183688
    Abstract: There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: May 22, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Yoshikawa, Motoo Suwa, Kazuyuki Sakata
  • Patent number: 8057676
    Abstract: Drainage water containing an organofluorine compound is introduced into a raw tank (1) and then filtered through a filtration device (4). Next, a microorganism, a micro-nanobubbling auxiliary agent and a nutrient are added thereto in a first transit tank (5) while micro-nanobubbles are generated thereinto by a micro-nanobubbling machine (7), thereby giving treated water. This treated water is then fed into an active carbon column (14) and then the above-described organofluorine compound contained in the treated water is decomposed by the microorganism as described above.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: November 15, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuyuki Yamasaki, Kazuyuki Sakata, Kazumi Chuhjoh, Masaki Kataoka
  • Patent number: 8043848
    Abstract: In a bioreactor, a culture solution derived from a cultivation tank is separated into bacteria cells and filtrate by a bacteria cell filter. The filtrate is introduced from the bacteria cell filter into a micro-nano bubble generation tank where micro-nano-bubbles are mixed with the filtrate. The filtrate containing micro-nano-bubbles is returned to the cultivation tank to activate the microorganisms therein, so that a biological reaction time is reduced by the activated microorganisms.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: October 25, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuyuki Yamasaki, Kazuyuki Sakata, Kazumi Chuhjoh, Masaki Kataoka
  • Patent number: 8034931
    Abstract: A process for producing a substituted aminoquinazolinone derivative of formula (I), characterized by reducing a substituted iminoquinazolinone derivative of formula (II) with hydrogen in the presence of a catalyst and either of a halogen compound and a sulfur compound; a substituted iminoquinazolinone derivative of formula (II?); and a pest control agent containing the derivative of formula (II?) or a salt thereof as an active ingredient and a method of using the same (in the formulae, R represents hydrogen, formyl, (C1-C6) alkyl, (C1-C6)alkoxy(C1-C3)alkyl, (C1-C6) alkylsulfonyl, optionally substituted phenylcarbonyl, etc.; R1 represents an optionally substituted, 5- or 6-membered heterocycle having one to three heteroatoms selected among oxygen, sulfur, and nitrogen; R2 represents hydrogen or (C1-C3) alkyl; X and X? may be the same or different and each represents (C1-C6) haloalkyl, (C1-C6) haloalkoxy, etc.; n is an integer of 0; and n? is an integer of 1-4).
    Type: Grant
    Filed: May 11, 2004
    Date of Patent: October 11, 2011
    Assignee: Nihon Nohyaku Co., Ltd.
    Inventors: Osamu Sanpei, Masahiro Uehara, Nobuyuki Niino, Hiroki Kodama, Kazuyuki Sakata
  • Publication number: 20110127671
    Abstract: There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip.
    Type: Application
    Filed: February 8, 2011
    Publication date: June 2, 2011
    Inventors: Yasuhiro Yoshikawa, Motoo Suwa, Kazuyuki Sakata
  • Patent number: 7945801
    Abstract: A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: May 17, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shigezumi Matsui, Takashi Sato, Kazuyuki Sakata, Tsuyoshi Yaguchi, Kenzo Kuwabara, Atsushi Nakamura, Motoo Suwa, Ryoichi Sano, Hisashi Shiota
  • Patent number: 7914677
    Abstract: Water (23) that contains micro-nano bubbles generated in a micro-nano bubble generation tank (6) is introduced and treated in a charcoal water tank (ii) which is filled with a charcoal (15) and in which an air diffusing pipe (12) is placed and thereafter introduced and treated in a membrane device (21). Thus, activities of microorganisms propagating in the charcoal (15) are increased by the micro-nano bubbles, markedly increasing ability of decomposing organic matters in the water. Therefore, a clogging phenomenon due to the organic matters can be prevented by reducing organic loads on the membrane device (21). Moreover, a very small amount of alcohols or salts are added as a micro-nano bubble generation aid to the micro-nano bubble generation tank (6), improving an incidence rate of the micro-nano bubbles. The alcohols and salts are easily decomposed by the charcoal water tank (ii) and easily removed by the membrane device (21).
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: March 29, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuyuki Yamasaki, Kazuyuki Sakata, Kazumi Chuhjoh
  • Patent number: 7888795
    Abstract: There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: February 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Yoshikawa, Motoo Suwa, Kazuyuki Sakata
  • Patent number: 7844934
    Abstract: According to the present invention, a method for designing a semiconductor integrated circuit layout comprises the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; arranging wiring between the basic logic cells; searching for a blank area in which none of the basic logic cells is arranged; extracting a rectangular region from the blank area; if the rectangular region is larger than a specified size, arranging fill cells in the rectangular region according to a predetermined rule and grouping the fill cells into pseudo-hierarchical cells according to a predetermined rule to form a hierarchy; arranging fill cells in the remaining blank areas; and performing optical proximity effect correction on the semiconductor integrated circuit pattern.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: November 30, 2010
    Assignees: Renesas Electronics Corporation, Panasonic Corporation, Fujitsu Microelectronics Limited, Kabushiki Kaisha Toshiba
    Inventors: Yusaku Ono, Osamu Suga, Kazuyuki Sakata, Hirofumi Taguchi, Yushi Okuno, Toshiaki Sugioka, Daisuke Kondo
  • Publication number: 20100244238
    Abstract: There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip.
    Type: Application
    Filed: June 7, 2010
    Publication date: September 30, 2010
    Inventors: Yasuhiro Yoshikawa, Motoo Suwa, Kazuyuki Sakata
  • Patent number: 7803272
    Abstract: A first treatment tank (1) to a fourth treatment tank are installed prior to ultrapure water production apparatus (5), dilute wastewater recovering apparatus (34), general service water recovering apparatus and wastewater treatment apparatus. The treatment tanks (1, 2, . . . ) each have a micro-nano bubble generation tank (6, 23, . . . ) and an anaerobic measuring tank (7, 24, . . . ). Accordingly, microbes within the respective anaerobic measuring tanks (7, 24, . . . ) are activated by micro-nano bubbles generated in each micro-nano bubble generation tank (6, 23, . . . ) to thereby enhance the treatment efficiency of low-concentration organic matter. Further, when the value measured by dissolved oxygen meter (13, 30, . . . ) or oxidation-reduction potentiometer (14, 31, . . . ) of each anaerobic measuring tank (7, 24, . . . ) exceeds an individually determined given range, the rotational speed of a circulating pump (9, 26, . . . ) is controlled to thereby decrease the generation of micro-nano bubbles.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: September 28, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuyuki Yamasaki, Kazuyuki Sakata, Kazumi Chuhjoh
  • Patent number: 7750464
    Abstract: There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: July 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yasuhiro Yoshikawa, Motoo Suwa, Kazuyuki Sakata