Patents by Inventor Kazuyuki Suga

Kazuyuki Suga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5832143
    Abstract: When a scan line is interpolated, pixels on scan lines above and below the scan line which are referenced is interpolated in the horizontal direction. These pixels on the upper and lower scan lines are divided into blocks. Correlations between the upper and lower blocks with respect to a target pixel to be interpolated are calculated. Based on an evaluating function which is formed based on the correlations but is corrected with reference to the distance (or the direction) from the target pixel to each of the blocks, an optimal interpolating direction is selected. In addition, the difference in the pixel data between the interpolated pixel and each of the pixels around the interpolated pixel is checked in order to find interpolation errors. When an interpolating pixel data is determined to be erroneous, the pixel is interpolated using the pixels of data above and below the pixel.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: November 3, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuyuki Suga, Hiroshi Kusao, Takashi Nishimura, Noritoshi Kakoh
  • Patent number: 5606321
    Abstract: A signal-processing circuit has the first reference-voltage setting circuit for setting a lower-limit reference voltage and an upper-limit reference voltage for the first A/D converter, a data-storing section for storing digital data obtained by the first A/D converter, and the second reference-voltage setting circuit for setting a lower-limit reference voltage for the second A/D converter to a voltage that is lower than the voltage corresponding to the digital data stored in the data-storing section and that is higher than the lower-limit reference voltage set by the first reference-voltage setting circuit, as well as for setting an upper-limit reference voltage for the second A/D converter to a voltage that is higher than the voltage corresponding to the digital data stored in the data-storing section and that is lower than the upper-limit reference voltage set by the first reference-voltage setting circuit.
    Type: Grant
    Filed: May 12, 1995
    Date of Patent: February 25, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazuyuki Suga
  • Patent number: 5474666
    Abstract: Water spotting which occurs during rinsing of an electrodeposited photosensitive resist composition on a copper layer of a printed circuit board is reduced by applying an aqueous solution containing a surfactant. The surfactant is preferably a salt of an acylated polypeptide which is solid at ambient room temperature and forms a thin uniform film when the solution is dried.
    Type: Grant
    Filed: November 24, 1993
    Date of Patent: December 12, 1995
    Assignee: Nippon Paint Co., Ltd.
    Inventors: Mamoru Seio, Kazuyuki Suga, Kanji Nishijima