Patents by Inventor Kazuyuki Sutou

Kazuyuki Sutou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8598720
    Abstract: A semiconductor device and its manufacturing method are offered to increase the number of semiconductor devices obtained from a semiconductor wafer while simplifying a manufacturing process. After forming a plurality of pad electrodes in a predetermined region on a top surface of a semiconductor substrate, a supporter is bonded to the top surface of the semiconductor substrate through an adhesive layer. Next, an opening is formed in the semiconductor substrate in a region overlapping the predetermined region. A wiring layer electrically connected with each of the pad electrodes is formed in the opening. After that, a stacked layer structure including the semiconductor substrate and the supporter is cut by dicing along a dicing line that is outside the opening.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: December 3, 2013
    Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Hiroaki Tomita, Kazuyuki Sutou
  • Patent number: 8193084
    Abstract: When a bump electrode is formed on an opening formed in a semiconductor substrate, the invention prevents a void that is caused by gas trapped in the opening. A method of manufacturing a semiconductor device of the invention includes forming a first wiring on a main surface of a semiconductor substrate, forming an opening in the semiconductor substrate from the back surface to the main surface so as to expose the back surface of the first wiring, forming a second wiring connected to the back surface of the first wiring and extending from inside the opening onto the back surface of the semiconductor substrate, forming a solder layer connected to part of the second wiring on the bottom of the opening and extending from inside the opening onto the back surface of the semiconductor substrate, and forming a bump electrode on the opening by reflowing the solder layer.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: June 5, 2012
    Assignees: Semiconductor Components Industries, LLC, SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd.
    Inventors: Kazuyuki Sutou, Hiroaki Tomita
  • Publication number: 20100130000
    Abstract: When a bump electrode is formed on an opening formed in a semiconductor substrate, the invention prevents a void that is caused by gas trapped in the opening. A method of manufacturing a semiconductor device of the invention includes forming a first wiring on a main surface of a semiconductor substrate, forming an opening in the semiconductor substrate from the back surface to the main surface so as to expose the back surface of the first wiring, forming a second wiring connected to the back surface of the first wiring and extending from inside the opening onto the back surface of the semiconductor substrate, forming a solder layer connected to part of the second wiring on the bottom of the opening and extending from inside the opening onto the back surface of the semiconductor substrate, and forming a bump electrode on the opening by reflowing the solder layer.
    Type: Application
    Filed: November 20, 2009
    Publication date: May 27, 2010
    Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd.
    Inventors: Kazuyuki Sutou, Hiroaki Tomita
  • Publication number: 20100102460
    Abstract: A semiconductor device and its manufacturing method are offered to increase the number of semiconductor devices obtained from a semiconductor wafer while simplifying a manufacturing process. After forming a plurality of pad electrodes in a predetermined region on a top surface of a semiconductor substrate, a supporter is bonded to the top surface of the semiconductor substrate through an adhesive layer. Next, an opening is formed in the semiconductor substrate in a region overlapping the predetermined region. A wiring layer electrically connected with each of the pad electrodes is formed in the opening. After that, a stacked layer structure including the semiconductor substrate and the supporter is cut by dicing along a dicing line that is outside the opening.
    Type: Application
    Filed: October 8, 2009
    Publication date: April 29, 2010
    Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd.
    Inventors: Hiroaki TOMITA, Kazuyuki SUTOU