Abstract: The present invention relates to an estimation system that can provide a highly reliable estimation result when the estimation system estimates person-hours required to prepare a film pattern for a circuit to be printed on a board. Upon receiving design conditions from a cline machine, a reference pin calculator of the estimation system calculates a number of reference pins on the basis of a total number of pins extending from parts to be integrated on the printed circuit board and a special specification requirement to be applied to the printed circuit. An additional pin calculator calculates a number of additional pins on the basis of a signal line wiring method. A total estimated pin calculator corrects a sum of the reference pins and the additional pins on the basis of design difficulty, which is determined from a number of signal layers to be made in the printed circuit, a number of signal lines arrangeable between adjacent pins and a pin density, to calculate a total estimated number of pins.

Abstract: In a system where a plurality of terminal units are connected to a network unit via an optical transmission line and packets are transmitted in units of cells according to polling information, polling request information including the number of variable-length packets stored in the buffer of each of the terminal unit, the number of cells composing each variable-length packet and the number of remaining cells of a packet being read is created, polling information corresponding to a time slot allocated according to the polling request information is transmitted from the shared band control unit of the network unit, and bands are allocated to the plurality of terminal units.

Abstract: The present invention relates to an estimation system that can provide a highly reliable estimation result when the estimation system estimates person-hours required to prepare a film pattern for a circuit to be printed on a board. Upon receiving design conditions from a cline machine, a reference pin calculator of the estimation system calculates a number of reference pins on the basis of a total number of pins extending from parts to be integrated on the printed circuit board and a special specification requirement to be applied to the printed circuit. An additional pin calculator calculates a number of additional pins on the basis of a signal line wiring method. A total estimated pin calculator corrects a sum of the reference pins and the additional pins on the basis of design difficulty, which is determined from a number of signal layers to be made in the printed circuit, a number of signal lines arrangeable between adjacent pins and a pin density, to calculate a total estimated number of pins.

Abstract: An optical switch device improving a yield and compact and excellent in expandability of optical incoming/outgoing ports, comprised of: a plurality of planar switch modules arranged in the horizontal direction and stacked in the vertical direction; and a coupler switch module, arranged in the vertical direction along each one side of the planar switch module, for selectively coupling the plurality of optical paths formed on one planar switch module and a plurality of optical paths formed on another planar switch module.

Abstract: A transmission circuit transmits a normal cell data and an idle cell data via a communication line. The idle cell data is transmitted to fill time slots in the communication line at which there is no normal data to be transmitted, each of the normal cell data and idle cell data including first data, second data and third data. The first, second and third data of the normal cell data respectively indicate a destination, an error correcting code of the first data and desired information. The first and second data of the idle cell data have predetermined bit patterns and the third data of the idle cell data may have any arbitrary bit pattern.

Abstract: A 1-bit error correction circuit based on CRC calculation is provided with a syndrome generation circuit which determines input parallel data of m bits and which have been converted from n number of m-bit serial data. A 1-bit error detection circuit cyclically supplies a syndrome to a remainder calculation circuit and decodes remainder data obtained from this cyclic supply and detects 1-bit errors. A actual data reproduction circuit calculates the exclusive OR of output data of a predetermined register of a 1'st.about.n'th register of a syndrome generation circuit and data supplied to a predetermined register and obtains parallel data which is the actual data. A correction circuit which calculates a exclusive OR of parallel data obtained from a actual data reproduction circuit and 1-bit error data detected by the 1-bit error detection circuit and outputs corrected data.

Abstract: A cross-connection apparatus for B-ISDN includes plural interface units, multiplexers, virtual path identifier (VPI) conversion tables, demultiplexers, and loop-back units and a switch unit.

Abstract: A system for monitoring an ATM cross-connecting apparatus by inputting a test cell through a path for a main signal into the ATM cross-connecting apparatus, and examining the cell after the cell passed through the ATM cross-connecting apparatus. An initial value of a PN sequence and the PN sequence generated based on the initial bit sequence is written in the test cell before inputting to the ATM cross-connecting apparatus. When examining the test cell, the initial bit sequence and the PN sequence are read from the cell, a PN sequence is generated based on the initial bit sequence, and the generated pseudo-noise sequence is then compared with the PN sequence read from the test cell to detect an error in the test cell. In addition, a bit pattern indicating a primitive polynomial to generate the PN sequence may be written in the test cell. In this case, the bit pattern is used for generating the PN sequence when examining the test cell.